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DAC34H84 データシート(PDF) 9 Page - Texas Instruments |
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DAC34H84 データシート(HTML) 9 Page - Texas Instruments |
9 / 96 page DAC34H84 www.ti.com SLAS751D – MARCH 2011 – REVISED SEPTEMBER 2015 Electrical Characteristics – DC Specifications (continued) over recommended operating free-air temperature range, nominal supplies, IOUTFS = 20mA (unless otherwise noted) (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEMPERATURE COEFFICIENTS Offset drift ±1 ppm/°C with external reference ±15 ppm/°C Gain drift with internal reference ±30 ppm/°C Reference voltage drift ±8 ppm/°C POWER SUPPLY(3) AVDD, IOVDD, PLLAVDD 3.14 3.3 3.46 V CLKVDD, DACVDD, DIGVDD 1.14 1.2 1.26 V IOVDD2 1.71 3.3 3.45 V PSRR Power supply rejection ratio DC tested ±0.25 %FSR/V POWER CONSUMPTION I(AVDD) Analog supply current(4) 135 165 mA MODE 1(5) I(DIGVDD) Digital supply current 740 820 mA fDAC = 1.25GSPS, 2x interpolation, Mixer on, I(DACVDD) DAC supply current 40 60 mA QMC on, invsinc on, PLL enabled, 20mA FS I(CLKVDD) Clock supply current 100 120 mA output, IF = 200MHz P Power dissipation 1500 1750 mW I(AVDD) Analog supply current(4) 125 mA MODE 2 I(DIGVDD) Digital supply current 740 mA fDAC = 1.25GSPS, 2x interpolation, Mixer on, I(DACVDD) DAC supply current 45 mA QMC on, invsinc on, PLL disabled, 20mA FS I(CLKVDD) Clock supply current 75 mA output, IF = 200MHz P Power dissipation 1440 mW I(AVDD) Analog supply current(4) 120 mA MODE 3 I(DIGVDD) Digital supply current 370 mA fDAC = 625MSPS, 2x interpolation, Mixer on, I(DACVDD) DAC supply current 25 mA QMC on, invsinc off, PLL disabled, 20mA FS I(CLKVDD) Clock supply current 45 mA output, IF = 200MHz P Power dissipation 925 mW I(AVDD) Analog supply current(4) 50 mA MODE 4 I(DIGVDD) Digital supply current 750 mA fDAC = 1.25GSPS, 2x interpolation, Mixer on, I(DACVDD) DAC supply current 40 mA QMC on, invsinc on, PLL enabled, Channels I(CLKVDD) Clock supply current 100 mA A/B/C/D output sleep, IF = 200MHz, P Power dissipation 1240 mW I(AVDD) Analog supply current(4) 40 mA Mode 5 I(DIGVDD) Digital supply current 10 mA Power-Down mode: No clock, DAC on sleep I(DACVDD) DAC supply current mode (clock receiver sleep), 5 mA Channels A/B/C/D output sleep, static data I(CLKVDD) Clock supply current 15 mA pattern P Power dissipation 150 mW I(AVDD) Analog supply current(4) 140 mA Mode 6 I(DIGVDD) Digital supply current 360 mA fDAC = 1GSPS, 2x interpolation, Mixer off, I(DACVDD) DAC supply current 30 mA QMC off, invsinc off, PLL enabled, 20mA FS I(CLKVDD) Clock supply current 90 mA output, IF = 200MHz P Power dissipation 1040 mW (3) To ensure power supply accuracy and to account for power supply filter network loss at operating conditions, the use of the ATEST function in register config27 to check the internal power supply nodes is recommended. (4) Includes AVDD, PLLAVDD, and IOVDD (5) PLL operation of 1.25GSPS in Mode 1 is used for maximum power consumption measurement only. Please follow the maximum DAC sample rate (FDAC) guideline in the AC Characteristic Table for proper DAC operation. Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: DAC34H84 |
同様の部品番号 - DAC34H84_15 |
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同様の説明 - DAC34H84_15 |
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