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SN74LV374APW データシート(PDF) 10 Page - Texas Instruments

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部品番号 SN74LV374APW
部品情報  Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs
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メーカー  TI1 [Texas Instruments]
ホームページ  http://www.ti.com
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SN74LV374APW データシート(HTML) 10 Page - Texas Instruments

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SN54LV374A, SN74LV374A
SCLS408I – APRIL 1998 – REVISED MARCH 2015
www.ti.com
8 Detailed Description
8.1 Overview
The SNx4LV374A devices are octal edge-triggered D-type flip-flops designed for 2-V to 5.5-V VCC operation.
These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively low-
impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bi-directional bus
drivers, and working registers. On the positive transition of the clock (CLK) input, the Q outputs are set to the
logic levels set up at the data (D) inputs. A buffered output-enable (OE) input can be used to place the eight
outputs in either a normal logic state (high or low logic levels) or high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased
drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect
internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the
high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to
VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of
the driver. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The output of the device is unknown until the first valid rising clock edge occurs while VCC is within the
Recommended Operating Conditions range.
8.2 Functional Block Diagram
Figure 4. Logic Diagram (Positive Logic)
8.3 Feature Description
The device’s wide operating range allows it to be used in a variety of systems that use different logic levels. The
low propagation delay allows fast switching and higher speeds of operation. In addition, the low ground bounce
stabilizes the performance of non-switching outputs while another output is switching.
8.4 Device Functional Modes
Table 1. Function Table (Each Flip-Flop)
INPUTS
OUTPUT
Q
OE
CLK
D
L
H
H
L
L
L
L
L
X
Q0
H
X
X
Z
10
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