SN74AUP1G125DRLR datasheet(4/36 Pages) TI1

部品番号	SN74AUP1G125DRLR

部品情報	Low-Power Single Bus Buffer Gate With 3-State Output

Download	36 Pages

Scroll/Zoom	100%

メーカー	TI1 [Texas Instruments]

ホームページ	http://www.ti.com

Logo

4 / 36 page

SN74AUP1G125

SCES595M – JULY 2004 – REVISED DECEMBER 2015

www.ti.com

Pin Functions

SOT-23,

I/O

DESCRIPTION

SON,

NAME

SC70, SOT,

DSBGA

A

2

I

Input

GND

3

—

Ground

N.C.

—

5

—

No connection

OE

1

I

Output Enable

VCC

5

6

—

Power terminal

Y

4

O

Output

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)

MIN

MAX

UNIT

VCC

Supply voltage

–0.5

4.6

V

VI

Input voltage(2)

–0.5

4.6

V

VO

Voltage applied to any output in the high-impedance or power-off state(2)

–0.5

4.6

V

VO

Output voltage in the high or low state(2)

–0.5

VCC + 0.5

V

IIK

Input clamp current

VI < 0

–50

mA

IOK

Output clamp current

VO < 0

–50

mA

IO

Continuous output current

±20

mA

Continuous current through VCC or GND

±50

mA

TJ

Junction temperature

–40

150

°C

Tstg

Storage temperature

–65

150

°C

(1)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

7.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)

2000

Electrostatic

V(ESD)

V

discharge

Charged-device model (CDM), per JEDEC specification JESD22-C101(2)

1000

(1)

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2)

JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

4

Submit Documentation Feedback

Product Folder Links: SN74AUP1G125

同様の部品番号 - SN74AUP1G125DRLR

メーカー	部品番号	データシート	部品情報
Texas Instruments	SN74AUP1G125DRLR	302Kb / 15P	[Old version datasheet] LOW-POWER SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT
	SN74AUP1G125DRLR	976Kb / 24P	[Old version datasheet] LOW-POWER SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT
	SN74AUP1G125DRLR	977Kb / 24P	[Old version datasheet] LOW-POWER SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT
	SN74AUP1G125DRLR	1Mb / 29P	[Old version datasheet] LOW-POWER SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT
	SN74AUP1G125DRLR	1Mb / 43P	[Old version datasheet] Low-Power Single Bus Buffer Gate With 3-State Output

More results

同様の説明 - SN74AUP1G125DRLR

メーカー	部品番号	データシート	部品情報
Texas Instruments	SN74AUP1G126	1Mb / 40P	[Old version datasheet] Low-Power Single Bus Buffer Gate With 3-State Output
	SN74AUP1G125	1Mb / 43P	[Old version datasheet] Low-Power Single Bus Buffer Gate With 3-State Output
	SN74AUP1G125YZTR	1Mb / 29P	[Old version datasheet] LOW-POWER SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT
	SN74AUP1G125	976Kb / 24P	[Old version datasheet] LOW-POWER SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT
	SN74AUP1G126	1,023Kb / 26P	[Old version datasheet] LOW-POWER SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT
	SN74AUP1G125_017	1Mb / 46P	[Old version datasheet] Low-Power Single Bus Buffer Gate With 3-State Output
	SN74AUP1G125	302Kb / 15P	[Old version datasheet] LOW-POWER SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT
	SN74AUP1G125_101	977Kb / 24P	[Old version datasheet] LOW-POWER SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT
	SN74AUP1G126	1Mb / 29P	[Old version datasheet] LOW-POWER SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT
	SN74AHC1G125	84Kb / 6P	[Old version datasheet] SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT