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SN74GTL2003PW データシート(PDF) 9 Page - Texas Instruments |
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SN74GTL2003PW データシート(HTML) 9 Page - Texas Instruments |
9 / 25 page SN74GTL2003 www.ti.com SCDS305B – FEBRUARY 2011 – REVISED JUNE 2015 8.4 Device Functional Modes Table 2. High to Low Translation (Assuming Dn is at the Higher Voltage Level)(1) INPUTS OUTPUT GREF (2) DREF SREF TRANSISTOR D8–D1 S8–S1 H H 0 V X X Off H H VTT (3) H VTT (4) On H H VTT L L(5) On L L 0 – VTT X X Off (1) H = HIGH voltage level, L = LOW voltage level, X = don't care. (2) GREF should be at least 1.5 V higher than SREF for best translator operation. (3) VTT is equal to the SREF voltage. (4) Sn is not pulled up or pulled down. (5) Sn follows the Dn input LOW. Table 3. Low to High Translation (Assuming Dn is at the Higher Voltage Level)(1) INPUTS OUTPUT GREF(2) DREF SREF TRANSISTOR D8–D1 S8–S1 H H 0 V X X Off H H VTT (3) VTT H(4) Nearly Off H H VTT L L(5) On L L 0 – VTT X X Off (1) H = HIGH voltage level, L = LOW voltage level, X = don't care. (2) GREF should be at least 1.5 V higher than SREF for best translator operation. (3) VTT is equal to the SREF voltage. (4) Dn is pulled up to VCC through an external resistor. (5) Dn follows the Sn input LOW. Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: SN74GTL2003 |
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