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74LVC2G125DCTRE4 データシート(PDF) 4 Page - Texas Instruments

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部品番号 74LVC2G125DCTRE4
部品情報  Dual Bus Buffer Gate With 3-State Outputs
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ホームページ  http://www.ti.com
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74LVC2G125DCTRE4 データシート(HTML) 4 Page - Texas Instruments

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SN74LVC2G125
SCES204P – APRIL 1999 – REVISED JANUARY 2016
www.ti.com
Product Folder Links: SN74LVC2G125
Submit Documentation Feedback
Copyright © 1999–2016, Texas Instruments Incorporated
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
The input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3)
The value of VCC is provided in the Recommended Operating Conditions table.
6 Specifications
6.1 Absolute Maximum Ratings
See
(1)
MIN
MAX
UNIT
VCC
Supply voltage range
–0.5
6.5
V
VI
Input voltage range(2)
–0.5
6.5
V
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
6.5
V
VO
Voltage range applied to any output in the high or low state (2)(3)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
Continuous current through VCC or GND
±100
mA
Tstg
Storage temperature range
–65
150
°C
TJ
Junction temperature
150
°C
(1)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2)
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings
PARAMETER
DEFINITION
VALUE
UNIT
V(ESD)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
2000
V
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins(2)
1000


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