データシートサーチシステム |
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TS80000 データシート(PDF) 6 Page - Semtech Corporation |
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TS80000 データシート(HTML) 6 Page - Semtech Corporation |
6 / 37 page SC80000 Final Datasheet Rev 1.4 March 17, 2015 www.semtech.com 6 of 37 Semtech Proprietary & Confidential I2C I/O Pins ALERT pin (optional): • Driven high when an event is active in the internal STATUS register • Driven low when all the internal events are cleared Note: The ALERT pin is provided to help with I2C communi- cation, i.e. to signal events to the App. MCU so the App. MCU can interrogate the TS80000 via I2C to see what changed on the wireless interface. The use of the ALERT pin is not mandatory in the application. SCL pin: • Clock pin for the I2C interface. • Open-drain with weak pull-ups. Needs stronger external pull-ups for full-speed operation. SDA pin: • Data pin for the I2C interface. • Open-drain with weak pull-ups. Needs stronger external pull-ups for full-speed operation. I2C Protocol The TS80000 Wireless Power Transmitter Controller acts as an I2C slave peripheral to allow communication with an application microcontroller. The slave address (7 bit) is 0x50. The Application MCU is an I2C master and initiates every data transfer. The TS80000 implements a set of registers available from the I2C bus. It also implements a set of API functions that receive parameters and return values using the I2C bus. Four transfer types are possible: • Write Register • Read Register • Run API Function • Read API Function Return Buffer START Start of the I2C transfer. M[S Slave Address (7 bits) 0 (1 bit) Slave ACK Slave address + R/nW bit (0xA0 as 8-bit) M[S Register n address (8 bits) Slave ACK Address of the first register M[S Register n Data (8 bits) Slave ACK Write the first register M[S Register n+1 Data (8 bits) Slave ACK Optionally write the following registers ... M[S Register n+k Data (8 bits) Slave ACK STOP Stop of the I2C transfer Write Register Operations Description START Start of the I2C transfer. M[S Slave Address (7 bits) 0 (1 bit) Slave ACK Slave address + 0 as R/nW bit (0xA0 as 8-bit) M[S Register n address (8 bits) Slave ACK Address of the first register START Repeated Start M[S Slave Address (7 bits) 1 (1 bit) Slave ACK Slave address + 1 as R/nW bit (0xA1 as 8-bit) S[M Register n Data (8 bits) Master ACK Read the first register S[M Register n+1 Data (8 bits) Master ACK Optionally read the following registers ... S[M Register n+k Data (8 bits) Master nACK The master should send a nACK after the last data byte was received. STOP Stop of the I2C transfer Read Register Operations Description |
同様の部品番号 - TS80000 |
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同様の説明 - TS80000 |
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