データシートサーチシステム |
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54F574FM データシート(PDF) 2 Page - National Semiconductor (TI) |
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54F574FM データシート(HTML) 2 Page - National Semiconductor (TI) |
2 / 8 page Connection Diagrams Pin Assignment for DIP SOIC and Flatpak TLF9567 – 2 Pin Assignment for LCC TLF9567 – 3 Functional Description The ’F574 consists of eight edge-triggered flip-flops with in- dividual D-type inputs and TRI-STATE true outputs The buffered clock and buffered Output Enable are common to all flip-flops The eight flip-flops will store the state of their individual D inputs that meet the setup and hold times re- quirements on the LOW-to-HIGH Clock (CP) transition With the Output Enable (OE) LOW the contents of the eight flip- flops are available at the outputs When OE is HIGH the outputs go to the high impedance state Operation of the OE input does not affect the state of the flip-flops Function Table Inputs Internal Outputs Function OE CP D Q O H H L NC Z Hold H H H NC Z Hold H L L L Z Load H L H H Z Load L L L L L Data Available L L H H H Data Available L H L NC NC No Change in Data L H H NC NC No Change in Data H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial Z e High Impedance L e LOW-to-HIGH Transition NC e No Change Logic Diagram TLF9567 – 5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays 2 |
同様の部品番号 - 54F574FM |
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同様の説明 - 54F574FM |
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