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LM1229 データシート(PDF) 6 Page - Texas Instruments |
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LM1229 データシート(HTML) 6 Page - Texas Instruments |
6 / 28 page OBSOLETE LM1229 SNOSAH0D – MARCH 2005 – REVISED APRIL 2013 www.ti.com DAC Output Electrical Characteristics Unless otherwise noted: TA = 25°C, VCC = +5.0V, VIN = 0.7V, VABL = VCC, CL = 10 pF, Video Outputs = 2.4 VP-P (1) (2). DAC parameters apply to all 3 DACs. Symbol Parameter Conditions Min Typ Max Units VDAC MIN Minimum DAC output voltage Register Value = 0x00 0.5 V VDAC MAX MODE 0 Maximum DAC output voltage Register Value = 0xFF, 4.2 V (full scale) GLOBAL[5] = 0 VDAC MAX MODE 1 Maximum DAC output voltage Register Value = 0xFF, 2.1 V (half scale) GLOBAL[5] = 1 ΔVDAC TEMP DAC output voltage variation with 0°C < T < 70°C ambient 0.5 mV/°C temperature ΔVDAC VCC 4.75V ≤ VCC ≤ 5.25V, DAC output voltage variation with VCC 50 mV DAC register set to mid-range (0x7F) Linearity Linearity of DAC over its range 5 % Monotonicity Monotonicity of the DAC excluding −0.5 +0.5 LSB dead zones IMAX Maximum DAC output load current 1.0 mA (1) Datasheet min/max specification limits are specified by design, test, or statistical analysis. The ensured specifications apply only for the test conditions listed. Some performance characteristics may change when the device is not operated under the listed test conditions. (2) Typical specifications are specified at +25°C and represent the most likely parametric norm. Deflection Signal Characteristics Unless otherwise noted: TA = 25°C, VCC = +5.0V, VIN = 0.7V, VABL = VCC, CL = 10 pF (1) (2) Symbol Parameter Conditions Min Typ Max Units fXTL Ceramic resonator input frequency 12 MHz VHFB Switching threshold for detecting 2.4 V horizontal flyback on pin 18 tFW Flyback Width 1 µs VVFB-DC DC bias point of VFB input 1.25 V VVFB-SW Switching threshold for detection 1.75 V VX-RAY Above VX-RAY the HDRIVE output is X-Ray Threshold Voltage 2.5 3.2 V disabled (high) VCCforXRAYRESET X-Ray Reset VCC required to reset X-Ray 4 V ΔfFR Free-run frequency tolerance (ceramic resonator tolerance) ±1 % fCR PLL capture range ±6 % tHDPHASE Horizontal phase control range All scan frequencies ±25 %TH tPARCOR Maximum parallelogram correction Measured at 31 kHz ±1 µs tBOWCOR Maximum pin balance (bow) Measured at 31 kHz ±0.5 µs correction HEHT− HEHT phase shift left (REHT = 20k) HEHT[3:0] = 0011b and V20 = 1.5V −2.7 %TH HEHT+ HEHT phase shift right (REHT = 20k) HEHT[3:0] = 0111b and V20 = 3.5V 2.8 %TH VHDOL HDRIVE Max low level output IOL = 10 mA 0.7 V IHDO HDRIVE Max sink current 10 mA VHDOH HDRIVE Max high level output voltage 5 V δ HDRIVE Duty cycle During normal use 50 % tON Delay to 50% duty cycle 60 lines tJITTER Jitter(3) Measured at 31 kHz scan frequency 1.8 ns fVMIN Minimum vertical lock frequency 50 Hz fVMAX Maximum vertical lock frequency 120 Hz (1) Datasheet min/max specification limits are specified by design, test, or statistical analysis. The ensured specifications apply only for the test conditions listed. Some performance characteristics may change when the device is not operated under the listed test conditions. (2) Typical specifications are specified at +25°C and represent the most likely parametric norm. (3) Jitter is measured at the 31 kHz scan rate by measuring the time difference between the leading edge of HSYNC and the leading edge of the HDRIVE output pulse. 6 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM1229 |
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