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LM1276 データシート(PDF) 10 Page - Texas Instruments

部品番号 LM1276
部品情報  Compatible RGB Preamplifier
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LM1276 データシート(HTML) 10 Page - Texas Instruments

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OBSOLETE
LM1276
SNOSAB9B – MAY 2005 – REVISED APRIL 2013
www.ti.com
SYSTEM INTERFACE SIGNALS
The Horizontal Sync, Flyback, Vertical Sync, and the Clamp input signals are important for proper functionality of
the LM1276. Both blanking inputs must be present for OSD synchronization. In addition, the Horizontal blanking
input also assists in setting the proper cathode black level, along with the Clamping pulse. The Vertical blanking
input initiates a blanking level at the LM1276 outputs, which is programmable from 3 to 127 lines (at least 10 is
recommended). This input is set up to only accept a vertical sync pulse, and the leading edge is used to start the
programmable vertical blanking signal directly. The start position of the internal Horizontal blanking pulse is
programmable from 0 to 64 pixels ahead of the start position of the Horizontal flyback input. Both horizontal and
vertical blanking can be individually disabled, if desired.
Figure 2 and Figure 3 show the Horizontal Flyback input when it is logic level and the Vertical input (which must
always be logic level). Figure 2 shows the smaller pin 28 voltage superimposed on the horizontal blanking pulse
input to the neck board with RH = 4.7k and C1 = 0.1 µF. Note where the voltage at pin 28 is clamped to about 1V
when the pin is sinking current. Figure 3 shows the smaller pin 1 voltage superimposed on the vertical blanking
input to the neck board with RV = 4.7k. These component values correspond to the application circuit of
Figure 10.
Please note that the Horizontal Flyback signal to pin 28 MUST be continuously provided to the IC, even during
energy save or sleep modes. In the application, this signal should be always generated whether the VGA cable is
disconnected, the monitor is in energy save mofe, or sleep mode.
Figure 4 show the case where the horizontal input is from deflection. Figure 4 shows the pin 28 voltage which is
derived from a horizontal flyback pulse of 35V peak to peak with RH = 8.2K and C1 jumpered.
Figure 5 shows the pin 27 clamp input voltage superimposed on the neck board clamp logic input pulse. R = 1k
and should be chosen to limit the pin 27 voltage to about 2.5V peak to peak. This corresponds to the application
circuit given in Figure 10. The clamp input pin can also be internally connected to the Horizontal Sync pin, thus
eliminating the need for a Clamp signal supplied to the neckboard. This can be enabled with register 0x853E[4].
H SYNC and V SYNC
V Sync at pin 1 and H Sync at pin 15 must be supplied with logic level signals generated by the MCU. In an
application where a logic level clamp pulse is used, the same signal can be used for the H Sync input. It is
important that both V Sync and H Sync are always receiving signals, even during VGA cable disconnect, energy
save mode, or sleep mode.
Cathode Response
Figure 6 shows the response at the red cathode for the application circuit in Figure 10 and Figure 11. The input
video rise time is 1.5 ns. The resulting leading edge has a 7.1 ns rise time and 7.6% overshoot, while the trailing
edge has a 7.1 ns rise time and 6.9% overshoot using an LM2467 driver.
ABL Gain Reduction
The ABL function reduces the contrast level of the LM1276 as the voltage on pin 26 is lowered from VCC to
around 2V. Figure 7 shows the amount of gain reduction as the voltage is lowered from VCC (5.0V) to 2V. The
gain reduction is small until V26 reaches the knee around 3.7V, where the slope increases. Many system designs
will require about 3 dB to 5 dB of gain reduction in full beam limiting. Additional attenuation is possible, and can
be used in special circumstances. However, in this case, video performance such as video linearity and tracking
between channels will tend to depart from normal specifications.
The onset of ABL in the LM1276 is adjustable so that the amount of beam limiting can be varied, especially for
larger Hi-Brite window displays where the contrast level is not desired to be reduced as much as a normal video
display. The beam current limiting is 4-bit adjustable in steps of 80 µA each all the way up to a delta of 1.2 mA.
The value of the ABL pull up resistor (R2) to the external +80V supply must be selected carefully such that the
ABL threshold current will be at the desired maximum (therefore, 2 mA) when register 0x85C4 is at the lowest
setting, 0x00.
10
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Product Folder Links: LM1276


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