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LM4548 データシート(PDF) 8 Page - Texas Instruments |
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LM4548 データシート(HTML) 8 Page - Texas Instruments |
8 / 21 page OBSOLETE LM4548 SNOS441C – FEBRUARY 1999 – REVISED APRIL 2013 www.ti.com PIN DESCRIPTIONS - ANALOG I/O (continued) Name Pin I / O Functional Description This line level input can be routed through the Input Mux and recorded by the right ADC. In addition, this analog input gets summed into the right output stream. The amount of VIDEO_R signal mixed in VIDEO_R 17 I the right output stream can be adjusted from +12dB to −34.5dB in 1.5dB steps as well as muted via register 14h. This line level input can be routed through the Input Mux and recorded by the left ADC. In addition, this analog input gets summed into the left output stream. The amount of CD_L signal mixed in the left CD_L 18 I output stream can be adjusted from +12dB to −34.5dB in 1.5dB steps as well as muted via register 12h. This input can be used to reject common mode signals on the CD_L and CD_R inputs. CD_GND is an CD_GND 19 I AC ground point and not a DC ground point. This input must be AC-coupled to the source signal's ground. This line level input can be routed through the Input Mux and recorded by the right ADC. In addition, this analog input gets summed into the right output stream. The amount of CD_R signal mixed in the CD_R 20 I right output stream can be adjusted from +12dB to −34.5dB in 1.5dB steps as well as muted via register 12h. Either MIC1 or MIC2 can be selected via software and routed through the Input Mux for recording. The 20dB boost circuit is enabled/disabled via register 0Eh. Also, the amount of mic signal mixed in the MIC1 21 I output stream can be adjusted from +12dB to −34.5dB in 1.5dB steps as well as muted via register 0Eh. Either MIC1 or MIC2 can be selected via software and routed through the Input Mux for recording. The 20dB boost circuit is enabled/disabled via register 0Eh. Also, the amount of mic signal mixed in the MIC2 22 I output stream can be adjusted from +12dB to −34.5dB in 1.5dB steps as well as muted via register 0Eh. This line level input can be routed through the Input Mux and recorded by the left ADC. In addition, this analog input gets summed into the left output stream. The amount of LINE_IN_L signal mixed in LINE_IN_L 23 I the left output stream can be adjusted from +12dB to −34.5dB in 1.5dB steps as well as muted via register 10h. This line level input can be routed through the Input Mux and recorded by the right ADC. In addition, this analog input gets summed into the right output stream. The amount of LINE_IN_R signal mixed in LINE_IN_R 24 I the right output stream can be adjusted from +12dB to −34.5dB in 1.5dB steps as well as muted via register 10h. This is a post-mixed output for the left audio channel. The level of this output can be adjusted from LINE_OUT_L 35 O 0dB to −45dB in 1.5dB steps as well as muted via register 02h. This is a post-mixed output for the right audio channel. The level of this output can be adjusted from LINE_OUT_R 36 O 0dB to −45dB in 1.5dB steps as well as muted via register 02h. This line level output is either the post-mixed output or the mic input. The level of this output can be MONO_OUT 37 O adjusted from 0dB to −45dB in 1.5dB steps as well as muted via register 06h. This is a post-mixed output for the left audio channel. The level of this output can be adjusted from LNLVL_OUT_L 39 O 0dB to −45dB in 1.5dB steps as well as muted via register 04h. This is a post-mixed output for the right audio channel. The level of this output can be adjusted from LNLVL_OUT_R 41 O 0dB to −45dB in 1.5dB steps as well as muted via register 04h. PIN DESCRIPTIONS - DIGITAL I/O AND CLOCKING Name Pin I / O Functional Description 24.576 MHz crystal input. Use a fundamental-mode type crystal. When operating from a crystal, a XTL_IN 2 I 1M Ω resistor must be connected across pins 2 and 3. 24.576 MHz crystal output. When operating from a crystal, a 1M Ω resistor must be connected across XTL_OUT 3 O pins 2 and 3. This data stream contains both control data and DAC audio data. This input is sampled by the LM4548 SDATA_OUT 5 I on the falling edge of BIT_CLK. OUTPUT when in Primary Codec Mode: This pin outputs a 12.288 MHz clock which is derived (internally divided by two) from the 24.576MHz crystal input (XTL_IN). BIT_CLK 6 I/O INPUT when in Secondary Codec Mode (Multiple Codec configurations only): 12.288MHz clock is to be supplied from an external source, such as from the BIT_CLK of a Primary Codec. This data stream contains both control data and ADC audio data. This output is clocked out by the SDATA_IN 8 O LM4548 on the rising edge of BIT_CLK. 48kHz sync pulse which signifies the beginning of both the SDATA_IN and SDATA_OUT serial SYNC 10 I streams. SYNC must be synchronous to BIT_CLK. 8 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LM4548 |
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同様の説明 - LM4548 |
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