データシートサーチシステム |
|
AD6674-750EBZ データシート(PDF) 10 Page - Analog Devices |
|
AD6674-750EBZ データシート(HTML) 10 Page - Analog Devices |
10 / 91 page AD6674 Data Sheet Timing Diagrams SERDOUT0– N – 54 N – 53 N – 52 N – 51 N – 1 SAMPLE N N + 1 APERTURE DELAY N – 55 CLK+ CLK– CLK+ CLK– SERDOUT0+ SERDOUT1– SERDOUT1+ SERDOUT2– SERDOUT2+ SERDOUT3– SERDOUT3+ A B C D E F G H I J A B C D E F G H I J A B C D E F G H I J A B C D E F G H I J A B C D E F G H I J A B C D E F G H I J A B C D E F G H I J A B C D E F G H I J A B C D E F G H I J A B C D E F G H I J A B C D E F G H I J A B C D E F G H I J CONVERTER0 MSB CONVERTER0 LSB CONVERTER1 MSB CONVERTER1 LSB ANALOG INPUT SIGNAL SAMPLE N – 55 ENCODED INTO 1 8-BIT/10-BIT SYMBOL SAMPLE N – 54 ENCODED INTO 1 8-BIT/10-BIT SYMBOL SAMPLE N – 53 ENCODED INTO 1 8-BIT/10-BIT SYMBOL Figure 2. Data Output Timing (VDR Mode; L = 4; M = 2; F = 1) CLK+ CLK– SYSREF+ SYSREF– tSU_SR tH_SR Figure 3. SYSREF± Setup and Hold Timing DON’T CARE DON’T CARE DON’T CARE DON’T CARE SDIO SCLK tS tDH tCLK tDS tH R/W A14 A13 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 tLOW tHIGH CSB Figure 4. Serial Port Interface Timing Diagram Rev. B | Page 10 of 91 |
同様の部品番号 - AD6674-750EBZ |
|
同様の説明 - AD6674-750EBZ |
|
|
リンク URL |
プライバシーポリシー |
ALLDATASHEET.JP |
ALLDATASHEETはお客様のビジネスに役立ちますか? [ DONATE ] |
Alldatasheetは | 広告 | お問い合わせ | プライバシーポリシー | リンク交換 | メーカーリスト All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |