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M02040-15 データシート(PDF) 1 Page - M/A-COM Technology Solutions, Inc.

部品番号 M02040-15
部品情報  3.3 5V Limiting Amplifier for Applications to 2.125 Gbps
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メーカー  MA-COM [M/A-COM Technology Solutions, Inc.]
ホームページ  http://www.macomtech.com
Logo MA-COM - M/A-COM Technology Solutions, Inc.

M02040-15 データシート(HTML) 1 Page - M/A-COM Technology Solutions, Inc.

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M/A-COM Technology Solutions Inc. (MACOM) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice.
Visit www.macom.com for additional data sheets and product information.
For further information and support please visit:
http://www.macom.com/support
M02040-15
1
3.3/5V Limiting Amplifier for Applications to 2.125 Gbps
Rev V4
Applications
• 1.0625 and 2.125 Gbps Fibre Channel
• 1.25 Gbps Ethernet
• 1.25 Gbps SDH/SONET
The M02040-15 is an integrated high-gain limiting amplifier. Featuring PECL outputs, the M02040-15 is useable in
applications to 2.125 Gbps. Full output swing is achieved even at minimum input sensitivity. The M02040-15 can
operate with a 3.3V or 5V supply.
DC_Servo supports applications requiring instantaneous output response.
The M02040-15 also includes two analog RSSI outputs proportional to either the average or peak to peak input sig-
nal and a programmable signal-level detector allowing the user to set thresholds at which the logic outputs are
enabled.
Other available solutions: M02050-15 3.3/5V Limiting Amplifier for Applications to 2.5 Gbps (PECL outputs)
M02049-15 3.3/5V Limiting Amplifier for Applications to 4.3 Gbps (CML outputs)
M02043-15 3.3/5V Limiting Amplifier for Applications to 4.3 Gbps (CML outputs)
1.25 Gbps and 4.25 Gbps SFP reference designs are available from your MACOM representative.
Typical Applications Diagram
T I A
Photodiode
+3.3 V
optional
Limiting
Amplifier
Comparator
Level
Shift
RSSIPP
DINN
RxAVGIN
RSSI
AVG
DINP
PECLN
PECLP
Offset cancel
Output
Buffer
Threshold
Setting
Circuit
Regulator
V
CC
ST
SET
V
CC3
IREF
Jam
LOS
AC-Coupled
to TIA
RST
DC_Servo
VTT
Level
Detect
AC or DC Coupled
(as described in
Applications Information)
Clock Data
Recovery
Unit
12.1 k
Ω
REXT
MON
M02016
DC_Servo Control
Biasing
Features
• Operates with a 3.3V or 5V supply
• 2 mV typical input sensitivity at 1.25 Gbps
• PECL outputs
• Average Receive power monitor output (RSSIAVG)
• Peak-to-peak Receive power monitor output (RSSIPP)
• On-chip DC offset cancellation circuit
• Offset cancellation circuit can be disabled for Burst mode applications
• Low power (170 mW at 3.3V)
• Output Jam function
• 16-pin 3x3 mm QFN package


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