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ADC1001CCJ-1 データシート(PDF) 6 Page - National Semiconductor (TI) |
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ADC1001CCJ-1 データシート(HTML) 6 Page - National Semiconductor (TI) |
6 / 9 page Timing Diagrams (Continued) Byte Sequencing For The 20-Pin ADC1001 Byte 8-Bit Data Bus Connection Order DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 MSB 1st Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 LSB 2nd Bit 1 Bit 0 000000 Functional Description The ADC1001 uses an advanced potentiometric resistive ladder network. The analog inputs, as well as the taps of this ladder network, are switched into a weighted capacitor array. The output of this capacitor array is the input to a sampled data comparator. This comparator allows the successive ap- proximation logic to match the analog difference input volt- age [V IN(+)−VIN(−)] to taps on the R network. The most sig- nificant bit is tested first and after 10 comparisons (80 clock cycles) a digital 10-bit binary code (all “1”s=full-scale) is transferred to an output latch and then an interrupt is as- serted (INTR makes a high-to-low transition). The device may be operated in the free-running mode by connecting INTR to the WR input with CS =0. To ensure start-up under all possible conditions, an external WR pulse is required dur- ing the first power-up cycle. A conversion in process can be interrupted by issuing a second start command. On the high-to-low transition of the WR input the internal SAR latches and the shift register stages are reset. As long as the CS input and WR input remain low, the A/D will remain in a reset state. Conversion will start from 1 to 8 clock peri- ods after at least one of these inputs makes a low-to-high transition. A functional diagram of the A/D converter is shown in Figure 3. All of the inputs and outputs are shown and the major logic control paths are drawn in heavier weight lines. The conversion is initialized by taking CS and WR simulta- neously low. This sets the start flip-flop (F/F) and the result- ing “1” level resets the 8-bit shift register, resets the Interrupt (INTR) F/F and inputs a “1” to the D flop, F/F1, which is at the input end of the 10-bit shift register. Internal clock signals then transfer this “1” to the Q output of F/F1. The AND gate, G1, combines this “1” output with a clock signal to provide a reset signal to the start F/F. If the set signal is no longer present (either WR or CS is a “1”) the start F/F is reset and the 10-bit shift register then can have the “1” clocked in, which allows the conversion process to continue. If the set signal were to still be present, this reset pulse would have no effect and the 10-bit shift register would continue to be held in the reset mode. This logic therefore allows for wide CS and WR signals and the converter will start after at least one of these signals returns high and the internal clocks again provide a reset signal for the start F/F. After the “1” is clocked through the 10-bit shift register (which completes the SAR search) it causes the new digital word to transfer to the TRI-STATE output latches. When this XFER signal makes a high-to-low transition the one shot fires, set- ting the INTR F/F. An inverting buffer then supplies the INTR output signal. Note that this SET control of the INTR F/F remains low for aproximately 400 ns. If the data output is continuously en- abled (CS and RD both held low), the INTR output will still signal the end of the conversion (by a high-to-low transition), because the SET input can control the Q output of the INTR F/F even though the RESET input is constantly at a “1” level. This INTR output will therefore stay low for the duration of the SET signal. When data is to be read, the combination of both CS and RD being low will cause the INTR F/F to be reset and the TRI-STATE output latches will be enabled. Zero and Full-Scale Adjustment Zero error can be adjusted as shown in Figure 1.V IN(+) is forced to +2.5 mV (+1⁄2 LSB) and the potentiometer is ad- justed until the digital output code changes from 00 0000 0000 to 00 0000 0001. Full-scale is adjusted as shown in Figure 2, with the V REF/2 input. With V IN (+) forced to the desired full-scale voltage less 11⁄2 LSBs (V FS−1 1 ⁄2 LSBs), V REF/2 is adjusted until the digital output code changes from 11 1111 1110 to 11 1111 1111. www.national.com 6 |
同様の部品番号 - ADC1001CCJ-1 |
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同様の説明 - ADC1001CCJ-1 |
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