The following specifications apply for V

Boldface limits apply for T

Symbol

Parameter

Conditions

Typical

Limit

Units

(Note 8)

(Note 9)

(Limits)

AC CHARACTERISTICS

f

C

Conversion Clock (C

0.7

MHz (min)

Frequency

4.0

3.0

MHz (max)

f

S

Serial Data Clock (S

183

kHz (min)

Frequency (Note 13)

f

622

kHz (min)

f

2

1.0

MHz (max)

T

C

Conversion Time

Not Including MUX Addressing and

41 (1/f

(max)

Analog Input Sampling Times

+ 200 ns

t

CA

Analog Sampling Time

After Address is Latched,CS = Low

4.5 (1/f

(max)

+ 200 ns

t

ACC

Access Time Delay from CS or OE

OE = “0”

100

200

ns (max)

Falling Edge to DO Data Valid

t

SET-UP

Set-up Time of CS Falling

75

150

ns (min)

Edge to S

t

Delay from OE or CS Rising

R

100

120

ns (max)

Edge to DO TRI-STATE

t

HDI

DI Hold Time from S

0

50

ns (min)

t

SDI

DI Set-up Time to S

50

100

ns (min)

t

HDO

DO Hold Time from S

R

70

10

ns (min)

t

DDO

Delay from S

R

150

250

ns (max)

Edge to DO Data Valid

t

RDO

DO Rise Time

R

TRI-STATE to High

35

75

ns (max)

C

Low to High

75

150

ns (max)

t

FDO

DO Fall Time

R

TRI-STATE to Low

35

75

ns (max)

C

High to Low

75

150

ns (max)

C

IN

Input Capacitance

Analog Inputs (CH0–CH7)

50

pF

All Other Inputs

7.5

pF

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.

Note 2: Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and

test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may de-

grade when the device is not operated under the listed test conditions.

Note 3: All voltages are measured with respect to AGND and DGND, unless otherwise specified.

maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four pins.

Note 6: Human body model, 100 pF capacitor discharged through a 1.5 k

Ω resistor.

Note 7: See AN450 “Surface Mounting Methods and Their Effect on Product Reliability” or Linear Databook section “Surface Mount” for other methods of soldering

surface mount devices.

Note 9: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).

Note 10: Total unadjusted error includes offset, full-scale, linearity, multiplexer, and hold step errors.

Note 11: Two on-chip diodes are tied to each analog input. They will forward-conduct for analog input voltages one diode drop below ground or one diode drop

evated temperatures, which will cause errors for analog inputs near full-scale. The spec allows 50 mV forward bias of either diode; this means that as long as the

perature variations, initial tolerance and loading.

Note 12: Channel leakage current is measured after the channel selection.

Note 13: In order to synchronize the serial data exchange properly, SARS needs to go low after completion of the serial I/O data exchange. If this does not occur

left-justified, and can be determined by the following equations:

f

www.national.com

3