Copyright

© ANPEC Electronics Corp.

Rev. A.1 - Dec., 2015

APW8855

www.anpec.com.tw

37

16.Application Information(Cont.)

Input Capacitor Selection

Use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the surge current needed

each time high-side MOSFET turns on. Place the small ceramic capacitors physically close to the MOSFETs and

between the drain of high-side MOSFET and the source of low-side MOSFET. The important parameters for the bulk

input capacitor are the voltage rating and the RMS current rating. For reliable operation, select the bulk capacitor with

voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The

capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of

1.5 times is a conservative guideline. The maximum RMS current rating requirement is approximately I

is the load current.

Layout Consideration

S ignal Nam e

De scription

La yout G uidelines

GND

IC

’s analog ground.

Connect the GND pin to GND plane through

several vias directly.

1V5_ALW_PGND,and

1V8_ALW_PGND

IC

’s power ground pins of VR3

and VR4.

Use a ground plane or a short and wide trace

to connect the ground terminals of input

capacitors

and

output

capacitors,

and

1Vx_ALW_PGND pins on top layer.

Each of VR

’s Input Pins

(VSYS, 1V8_ALW_IN...)

All VR

’s input voltage pins.

Place the input capacitors on each of the VR

’s

input pins with low impedance to GND and low

impedance to the each of VR

’s input pins.

Each of PWM VR

’s LX pins

(5V_ALW_LX1,

1V8_ALW_LX

…)

These are the connections to the

mid point of the power stage

consisting

of

the

high-

and

low-side

switch.

The

output

inductor is connected here.

Connect to the output inductor with a short

wire.

For higher efficiency requirement, the

inductor and LX pins should be as close as

possible, and the trace resistance from LX pin

to inductor should be less than 10mOhm is

recommended.

Ideally, route the high current path like LX pins

to inductors and inductors to output capacitors

on the top layer is recommended.

Each of PWM VR

’s output

voltage feedback pins

(5V_ALW_FBP,

1V8_ALW_FBP

…)

Voltage feedback pin for each of

VR.

The pins are high impedance and sensible to

noise from the switch node. The positive

feedback signal should be tied to the V+ pad

of the output capacitor directly.

The feedback pin could be routed to the input

capacitor on the load side for remote sense.

Coupling from fast switching signals must be

avoided.

VSYS

APW8855 input supply voltage

Connect the input capacitors from VSYS to

GND for noise decoupling. The capacitors and

VSYS pins should be as close as possible.

5V_ALW_PWM,

3V3_ALW_PWM,

VDDP_ALW_PWM

The

gate

driver

outputs

of

5V_ALW,

3V3_ALW

and

VDDP_ALW

The traces of PWM signal from the gate driver

output pins to the APW8703 should be short to

eliminate the parasitical capacitance; the

parasitical capacitance less than 80pF is

recommended.