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AD7091R-2BRUZ-RL7 データシート(PDF) 9 Page - Analog Devices

部品番号 AD7091R-2BRUZ-RL7
部品情報  2-/4-/8-Channel, 1 MSPS, Ultralow Power, 12-Bit SAR ADC
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ホームページ  http://www.analog.com
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AD7091R-2BRUZ-RL7 データシート(HTML) 9 Page - Analog Devices

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Data Sheet
AD7091R-2/AD7091R-4/AD7091R-8
Rev. C | Page 9 of 42
Figure 7. 4-Channel, 20-Lead TSSOP Pin Configuration
Figure 8. 4-Channel, 20-Lead LFCSP Pin Configuration
Table 6. 4-Channel, 20-Lead LFCSP and 20-Lead TSSOP Pin Function Descriptions
Pin No.
Mnemonic
Description
TSSOP
LFCSP
1
19
CS
Chip Select Input. When CS is held low, the serial bus enables, and CS frames the output data on
the SPI.
2
20
RESET
Reset. Logic input.
3
1
VDD
Power Supply Input. The VDD range is from 2.7 V to 5.25 V. Decouple this supply pin to GND.
4
2
REGCAP
Decoupling Capacitor Pin for Voltage Output from Internal Regulator. Decouple this output pin
separately to GND using a 1.0 μF capacitor.
5
3
REFIN/REFOUT
Voltage Reference Output, 2.5 V. Decouple this pin to GND. Typical recommended decoupling
capacitor value is 2.2 μF. The user can either access the internal 2.5 V reference or overdrive the
internal reference with the voltage applied to this pin. The reference voltage range for an
externally applied reference is 1.0 V to VDD.
6, 15
4, 13
GND
Chip Ground Pins. These pins are the ground reference point for all circuitry on the AD7091R-4.
7
5
MUXOUT
Multiplexer Output. The output of the multiplexer appears at this pin. If no external filtering or
buffering is required, tie this pin directly to the ADCIN pin; otherwise, tie the output of the
conditioning network to the ADCIN pin.
8
6
VIN0
Analog Input 0. Single-ended analog input. The analog input range is 0 V to VREF.
9
7
VIN2
Analog Input 2. Single-ended analog input. The analog input range is 0 V to VREF.
10
8
ALERT/BUSY/GPO0
Alert Output Pin (ALERT). This is a multifunction pin determined by the configuration register.
When functioning as ALERT, this pin is a logic output indicating that a conversion result has
fallen outside the limit of the register settings.
When the ALERT/BUSY/GPO0 pin is configured as a BUSY output, use this pin to indicate when a
conversion is taking place.
The pin can also function as a general-purpose digital output.
11
9
GPO1
General-Purpose Digital Output.
12
10
VIN3
Analog Input 3. Single-ended analog input. The analog input range is 0 V to VREF.
13
11
VIN1
Analog Input 1. Single-ended analog input. The analog input range is 0 V to VREF.
14
12
ADCIN
ADC Input. This pin allows access to the on-chip track-and-hold. If no external filtering or
buffering is required, tie this pin directly to the MUXOUT pin; otherwise, tie the input of the
conditioning network to the MUXOUT pin.
16
14
SDI
Serial Data Input Bus. This input provides data written to the on-chip control registers. Data
clocks into the registers on the falling edge of the SCLK input. Provide data MSB first.
17
15
SDO
Serial Data Output Bus. The conversion output data is supplied to this pin as a serial data
stream. The bits are clocked out on the falling edge of the SCLK input, and 13 SCLKs are
required to access the data. The data is provided MSB first.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
AD7091R-4
TOP VIEW
(Not to Scale)
RESET
VDD
REGCAP
MUXOUT
GND
CS
VIN0
VIN2
ALERT/BUSY/GPO0
CONVST
SCLK
SDO
ADCIN
GND
SDI
VIN1
VIN3
GPO1
VDRIVE
REFIN/REFOUT
14
13
12
1
3
4
15
11
2
5
VDD
REGCAP
MUXOUT
GND
REFIN/REFOUT
ADCIN
GND
SDI
VIN1
SDO
AD7091R-4
TOP VIEW
(Not to Scale)
NOTES
1. THE EXPOSED PAD IS NOT CONNECTED
INTERNALLY. IT IS RECOMMENDED THAT
THE PAD BE SOLDERED TO GND.


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