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AD7175-8BCPZ データシート(PDF) 3 Page - Analog Devices |
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AD7175-8BCPZ データシート(HTML) 3 Page - Analog Devices |
3 / 64 page Data Sheet AD7175-8 Rev. 0 | Page 3 of 64 SPECIFICATIONS AVDD1 = 4.5 V to 5.5 V, AVDD2 = 2 V to 5.5 V, IOVDD = 2 V to 5.5 V, AVSS = DGND = 0 V, REF+ = 2.5 V, REF− = AVSS, internal master clock (MCLK) = 16 MHz, TA = TMIN to TMAX (−40°C to +105°C), unless otherwise noted. Table 1. Parameter Test Conditions/Comments Min Typ Max Unit ADC SPEED AND PERFORMANCE Output Data Rate (ODR) 5 250,000 SPS No Missing Codes1 Excluding sinc3 filter ≥ 125 kSPS 24 Bits Resolution See Table 19 to Table 23 Noise See Table 19 to Table 23 ACCURACY Integral Nonlinearity (INL) All input buffers enabled ±4.5 10 ppm of FSR All input buffers disabled ±1 ±4.5 ppm of FSR Offset Error2 Internal short ±60 µV Offset Drift Internal short ±150 nV/°C Gain Error2 ±80 ±110 ppm of FSR Gain Drift1 ±0.5 ±0.75 ppm/°C REJECTION Power Supply Rejection AVDD1, AVDD2, for V IN = 1 V 90 dB Common-Mode Rejection V IN = 0.1 V At DC 95 dB At 50 Hz, 60 Hz1 20 Hz output data rate (post filter), 50 Hz ± 1 Hz and 60 Hz ± 1 Hz 120 dB Normal Mode Rejection1 50 Hz ± 1 Hz and 60 Hz ± 1 Hz Internal clock, 20 SPS ODR (postfilter) 71 90 dB External clock, 20 SPS ODR (postfilter) 85 90 dB ANALOG INPUTS Differential Input Range V REF = (REF+) − (REF−) ±V REF V Absolute Voltage Limits1 Input Buffers Disabled AVSS − 0.05 AVDD1 + 0.05 V Input Buffers Enabled AVSS AVDD1 V Analog Input Current Input Buffers Disabled Input Current ±48 µA/V Input Current Drift External clock ±0.75 nA/V/°C Internal clock ±4 nA/V/°C Input Buffers Enabled Input Current ±30 nA Input Current Drift AVDD1 − 0.2 V to AVSS + 0.2 V ±75 pA/°C AVDD1 to AVSS ±1 nA/°C Crosstalk 1 kHz input −120 dB INTERNAL REFERENCE 100 nF external capacitor to AVSS Output Voltage REFOUT, with respect to AVSS 2.5 V Initial Accuracy3 REFOUT, T A = 25°C −0.12 +0.12 % of V Temperature Coefficient1 0°C to 105°C ±2 ±5 ppm/°C −40°C to +105°C ±3 ±10 ppm/°C Reference Load Current, I LOAD −10 +10 mA Power Supply Rejection AVDD1, AVDD2 (line regulation) 95 dB Load Regulation ∆V OUT/∆ILOAD 32 ppm/mA Voltage Noise e N, 0.1 Hz to 10 Hz, 2.5 V reference 4.5 µV rms Voltage Noise Density e N, 1 kHz, 2.5 V reference 215 nV/√Hz |
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