AD7768-4BSTZ-RL7 datasheet(1/99 Pages) AD

部品番号	AD7768-4BSTZ-RL7

部品情報	8-/4-Channel, 24-Bit, Simultaneous Sampling ADCs with Power Scaling, 110.8 kHz BW

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8-/4-Channel, 24-Bit, Simultaneous Sampling

ADCs with Power Scaling, 110.8 kHz BW

Data Sheet

AD7768/AD7768-4

Rev. A

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FEATURES

Precision ac and dc performance

8-/4-channel simultaneous sampling

256 kSPS maximum ADC output data rate per channel

108 dB dynamic range

110.8 kHz maximum input bandwidth (−3 dB bandwidth)

−120 dB total harmonic distortion (THD) typical

±2 ppm of full-scale range (FSR) integral nonlinearity

(INL), ±50 µV offset error, ±30 ppm gain error

Optimized power dissipation vs. noise vs. input bandwidth

Selectable power, speed, and input bandwidth (BW) modes

Fast: highest speed; 110.8 kHz BW, 51.5 mW per channel

Median: half speed, 55.4 kHz BW, 27.5 mW per channel

Eco: lowest power, 13.8 kHz BW, 9.375 mW per channel

Input BW range: dc to 110.8 kHz

Programmable input bandwidth/sampling rates

Cyclic redundancy check (CRC) error checking on data interface

Daisy-chaining

Linear phase digital filter

Low latency sinc5 filter

Wideband brick wall filter: ±0.005 dB pass-band ripple

from dc to 102.4 kHz

Analog input precharge buffers

Power supply

AVDD1 = 5.0 V, AVDD2 = 2.25 V to 5.0 V

IOVDD = 2.5 V to 3.3 V or IOVDD = 1.8 V

64-lead LQFP package, no exposed pad

Temperature range: −40°C to +105°C

APPLICATIONS

Data acquisition systems: USB/PXI/Ethernet

Instrumentation and industrial control loops

Audio test and measurement

Vibration and asset condition monitoring

3-phase power quality analysis

Sonar

High precision medical electroencephalogram (EEG)/

electromyography (EMG)/electrocardiogram (ECG)

FUNCTIONAL BLOCK DIAGRAM

ADC

OUTPUT

DATA

SERIAL

INTERFACE

DIGITAL

FILTER

ENGINE

WIDEBAND

LOW RIPPLE

FILTER

SINC5

LOW LATENCY

FILTER

SPI

CONTROL

INTERFACE

1.8V

LDO

SYNC_IN

1.8V

LDO

BUFFERED

VCM

AIN1+

CH 1

AIN1–

AIN2+

CH 2

AIN2–

AIN3+

CH 3

AIN3–

AIN4+

CH 4*

AIN4–

AIN5+

CH 5*

AIN5–

AIN6+

CH 6*

AIN6–

AIN7+

CH 7*

AIN7–

AIN0+

CH 0

AIN0–

VCM

×8

PRECHARGE

REFERENCE

BUFFERS

SYNC_OUT

START

RESET

FORMAT1*

FORMAT0

DRDY

DCLK

ST0/CS

PIN/SPI

ST1*/SCLK

DEC0/SDO

DEC1/SDI

AVSS

XTAL2/MCLK

XTAL1

MODE3/GPIO3

TO

MODE0/GPIO0

FILTER/GPIO4

Σ-Δ

ADC

Σ-Δ

ADC

Σ-Δ

ADC

Σ-Δ

ADC

Σ-Δ

ADC

Σ-Δ

ADC

Σ-Δ

ADC

Σ-Δ

ADC

DOUT7*

AVDD1A,

AVDD1B

DGND

AD7768/AD7768-4

IOVDD

DREGCAP

REGCAPA,

REGCAPB

AVDD2A,

AVDD2B

REFx+ REFx–

OFFSET,

GAIN PHASE

CORRECTION

OFFSET,

GAIN PHASE

CORRECTION

OFFSET,

GAIN PHASE

CORRECTION

OFFSET,

GAIN PHASE

CORRECTION

OFFSET,

GAIN PHASE

CORRECTION

OFFSET,

GAIN PHASE

CORRECTION

OFFSET,

GAIN PHASE

CORRECTION

OFFSET,

GAIN PHASE

CORRECTION

DOUT1

DOUT0

DOUT2

DOUT3

DOUT4*

DOUT5*

DOUT6*, DIN

*THESE CHANNELS/PINS EXIST ONLY ON THE AD7768.

P

×16 ANALOG INPUT

PRECHARGE BUFFERS (P)

Figure 1.

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