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ADuM4150BRIZ-RL データシート(PDF) 9 Page - Analog Devices

部品番号 ADuM4150BRIZ-RL
部品情報  5 kV, 6-Channel, SPIsolator Digital
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ホームページ  http://www.analog.com
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ADuM4150BRIZ-RL データシート(HTML) 9 Page - Analog Devices

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Data Sheet
ADuM4150
ELECTRICAL CHARACTERISTICS—MIXED 3.3 V/5 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = 3.3 V and VDD2 = 5 V. Minimum and maximum specifications apply over the entire
recommended operation range: 3.0 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching
specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
Table 8. Switching Specifications
Parameter
Symbol
A Grade
B Grade
Unit
Test Conditions/Comments
Min
Typ
Max
Min
Typ
Max
MCLK, MO, SO
SPI Clock Rate
SPIMCLK
9.2
15.6
MHz
Data Rate Fast (MO, SO)
DRFAST
40
40
Mbps
Within PWD limit
Propagation Delay
tPHL, tPLH
27
16
ns
50% input to 50% output
Pulse Width
PW
12.5
12.5
ns
Within PWD limit
Pulse Width Distortion
PWD
2
2
ns
|tPLH − tPHL|
Codirectional Channel Matching1
tPSKCD
3
3
ns
Jitter, High Speed
JHS
1
1
ns
MSS
Data Rate Fast
DRFAST
40
40
Mbps
Within PWD limit
Propagation Delay
tPHL, tPLH
26
26
ns
50% input to 50% output
Pulse Width
PW
12.5
12.5
ns
Within PWD limit
Pulse Width Distortion
PWD
3
3
ns
|tPLH − tPHL|
Setup Time2
MSSSETUP
1.5
10
ns
Jitter, High Speed
JHS
1
1
ns
DCLK3
Data Rate
40
40
MHz
Propagation Delay
tPHL, tPLH
60
40
ns
tPMCLK + tPSO + 3 ns
Pulse Width Distortion
PWD
3
3
ns
|tPLH − tPHL|
Pulse Width
PW
12
12
ns
Within PWD limit
Clock Delay Error
DCLKERR
2
7
13
2
6.8
11
ns
tPDCLK − (tPMCLK + tPSO)
Jitter
JDCLK
1
1
ns
VIA, VIB
Data Rate Slow
DRSLOW
250
250
kbps
Within PWD limit
Propagation Delay
tPHL, tPLH
0.1
2.6
0.1
2.6
µs
50% input to 50% output
Pulse Width
PW
4
4
µs
Within PWD limit
Jitter, Low Speed
JLS
2.5
2.5
µs
VIx4 Minimum Input Skew5
tVIx SKEW
10
10
ns
1
Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier.
2
The MSS signal is glitch filtered in both speed grades, whereas the other fast signals are not glitch filtered in the B grade. To guarantee that MSS reaches the output
ahead of another fast signal, set up MSS prior to the competing signal by different times depending on speed grade.
3
tPMCLK is the propagation delay of the MCLK signal from Side 1 to Side 2. tPSO is the propagation delay of the SO signal from Side 2 to Side 1. tPDCLK is the difference
between the DCLK signal and the round trip propagation delay.
4
VIx = VIA or VIB.
5
An internal asynchronous clock, not available to users, samples the low speed signals. If edge sequence in codirectional channels is critical to the end application, the
leading pulse must be at least 1 tVIx SKEW time ahead of a later pulse to guarantee the correct order or simultaneous arrival at the output.
Rev. A | Page 9 of 21


同様の部品番号 - ADuM4150BRIZ-RL

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