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MTV003 データシート(PDF) 5 Page - List of Unclassifed Manufacturers |
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MTV003 データシート(HTML) 5 Page - List of Unclassifed Manufacturers |
5 / 13 page MYSON TECHNOLOGY MTV003N (MTV003) MTV003 Revision 2.3 07/01/1998 5/13 V-Freq(Hz) Output value hexadecimal 9 bits decimal Tolerance (%) 1 20 30D 781 0.12804 2 56.25 115 277 0.36101 3 59.94 104 260 0.38461 4 60 104 260 0.38461 5 60.32 103 259 0.38610 6 60.53 102 258 0.38759 7 66.67 0EA 234 0.42735 8 70.069 0DE 222 0.45045 9 70.08 0DE 222 0.45045 10 72 0D9 217 0.46082 11 72.378 0D7 215 0.46511 12 72.7 0D6 214 0.46728 13 87 0B3 179 0.55865 3.6 Command Interface The command interface contains 3 pins. Each transfer of command is comprised of 16 DCK clock periods. The first 8 DCK clocks are for the address and direction of DIO, and the succeeding 8 DCK clocks are for the data. Each transfer is initiated by setting CMDB Low. The CMDB pin must be pulled High after data transfer is completed. - Command Format B0 - 4 ( ADD4 - 0) : Address of the registers. B5 ( W/RB) : Transfer direction, 1=write, 0=read. B6 - 7 : Reserved. B8 - 15 ( DA0 - 7) : Data input when W/RB=1. ( DA7 - 0) Data output when W/RB=0. - Register Allocation a. Read Transfer Address Portion Data Portion ADD4-0 W/RB DA7 - 0 Reg # B0 - 4 B5 B8 B9 B10 B11 B12 B13 B14 B15 Reg0 00000 0 Hpol Vpol HSpre VSpre HVpre Hsl Vsl x Reg1 00001 0 x x x x HCFF HF10 HF9 HF8 Reg2 00010 0 HF7 HF6 HF5 HF4 HF3 HF2 HF1 HF0 Reg3 00011 0 xxx xxx VCFF VF8 Reg4 00100 0 VF7 VF6 VF5 VF4 VF3 VF2 VF1 VF0 Table 4 b. Write Transfer Address Portion Data Portion ADD4-0 W/RB DA0 - 7 Reg # B0 - 4 B5 B8 B9 B10 B11 B12 B13 B14 B15 Reg0 00000 1 xxxxxx x x Reg1 00001 1 Vpf0 Vpf1 Hpf0 Hpf1 VBpl HBpl HVcvs x Reg2 00010 1 xxxxxx x x Reg3 00011 1 CLK4M TEST xxxx x x |
同様の部品番号 - MTV003 |
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同様の説明 - MTV003 |
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