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TDA7330 データシート(PDF) 4 Page - STMicroelectronics |
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TDA7330 データシート(HTML) 4 Page - STMicroelectronics |
4 / 9 page OUTPUT TIMING The generated 1187.5Hz output clock (RDCL line) is synchronized to the incoming data. According to the internal PLL lock condition this data change can results on the falling or on the rising clock edge. Whichever clock edge is used by the decoder (ris- ing or falling edge) the data will remain valid for 416.7 µsec after the clock transition. Figure 2: RDS timing diagram Figure 3: Test Circuit Measure f1 (KHz) f2 (KHz) f3 (KHz) ∆Ph max A 56.5 57 57.5 <5 ° B 565758 <7.5 ° C 55.5 57 58.5 <10 ° Note(2): The 3th harmonic (57KHz) must be less than -40dB in respect to the input signal 19KHz plus gain. ELECTRICAL CHARACTERISTICS (continued) TDA7330B 4/9 |
同様の部品番号 - TDA7330 |
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同様の説明 - TDA7330 |
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