 |
データシートサーチシステム |
|
|
データシートサーチシステム |
|
FM25V02A-G データシート(PDF) 5 Page - Cypress Semiconductor |
|
||||||||||||||||||||||||||||||
FM25V02A-G データシート(HTML) 5 Page - Cypress Semiconductor |
|
|
5 / 23 page  FM25V02A Document Number: 001-90865 Rev. *F Page 5 of 23 For a microcontroller that has no dedicated SPI bus, a general-purpose port may be used. To reduce hardware resources on the controller, it is possible to connect the two data pins (SI, SO) together and tie off (HIGH) the HOLD and WP pins. Figure 4 shows such a configuration, which uses only three pins. Most Significant Bit (MSB) The SPI protocol requires that the first bit to be transmitted is the Most Significant Bit (MSB). This is valid for both address and data transmission. The 256-Kbit serial F-RAM requires a 2-byte address for any read or write operation. Because the address is only 15 bits, the upper bit which is fed in is ignored by the device. Although the upper bit is ‘don’t care’, Cypress recommends that these bits be set to 0s to enable seamless transition to higher memory densities. Serial Opcode After the slave device is selected with CS going LOW, the first byte received is treated as the opcode for the intended operation. FM25V02A uses the standard opcodes for memory accesses. Invalid Opcode If an invalid opcode is received, the opcode is ignored and the device ignores any additional serial data on the SI pin until the next falling edge of CS, and the SO pin remains tristated. Status Register FM25V02A has an 8-bit Status Register. The bits in the Status Register are used to configure the device. These bits are described in Table 3 on page 7. SPI Modes FM25V02A may be driven by a microcontroller with its SPI peripheral running in either of the following two modes: ■ SPI Mode 0 (CPOL = 0, CPHA = 0) ■ SPI Mode 3 (CPOL = 1, CPHA = 1) For both these modes, the input data is latched in on the rising edge of SCK starting from the first rising edge after CS goes active. If the clock starts from a HIGH state (in mode 3), the first rising edge after the clock toggles is considered. The output data is available on the falling edge of SCK.The two SPI modes are shown in Figure 5 on page 6 and Figure 6 on page 6. The status of the clock when the bus master is not transferring data is: ■ SCK remains at 0 for Mode 0 ■ SCK remains at 1 for Mode 3 Figure 3. System Configuration with SPI Port Figure 4. System Configuration Without SPI Port CS 1 CS 2 HO L D 1 HO L D 2 FM25V02A FM25V02A WP1 WP2 SCK SI SO SCK SI SO CS HOLD WP CS HOLD WP SCK MOSI MISO SPI Microcontroller FM25V02A Microcontroller SCK SI SO CS HOLD WP P1.2 P1.1 P1.0 |
同様の部品番号 - FM25V02A-G |
|
同様の説明 - FM25V02A-G |
|
|
|
リンク URL |
| プライバシーポリシー |
| ALLDATASHEET.JP |
| ALLDATASHEETはお客様のビジネスに役立ちますか？ [ DONATE ] |
Alldatasheetは | 広告 | お問い合わせ | プライバシーポリシー | リンク交換 | メーカーリスト All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Japanese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
