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FM25V40 データシート(PDF) 7 Page - Cypress Semiconductor |
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FM25V40 データシート(HTML) 7 Page - Cypress Semiconductor |
7 / 23 page PRELIMINARY FM25V40 Document Number: 001-87288 Rev. *A Page 7 of 23 Status Register and Write Protection The write protection features of the FM25V40 are multi-tiered and are enabled through the status register. The Status Register is organized as follows. (The default value shipped from the factory for bit 0, WEL, BP0, BP1, bits 4–5, WPEN is ‘0’, and for bit 6 is ‘1’). Bits 0 and 4-5 are fixed at ‘0’ and bit 6 is fixed at ‘1’; none of these bits can be modified. Note that bit 0 ("Ready or Write in progress” bit in serial flash and EEPROM) is unnecessary, as the F-RAM writes in real-time and is never busy, so it reads out as a ‘0’. An exception to this is when the device is waking up from sleep mode, which is described in Sleep Mode on page 11. The BP1 and BP0 control the software write-protection features and are nonvolatile bits. The WEL flag indicates the state of the Write Enable Latch. Attempting to directly write the WEL bit in the Status Register has no effect on its state. This bit is internally set and cleared via the WREN and WRDI commands, respectively. BP1 and BP0 are memory block write protection bits. They specify portions of memory that are write-protected as shown in Table 4. The BP1 and BP0 bits and the Write Enable Latch are the only mechanisms that protect the memory from writes. The remaining write protection features protect inadvertent changes to the block protect bits. The write protect enable bit (WPEN) in the Status Register controls the effect of the hardware write protect (WP) pin. When the WPEN bit is set to '0', the status of the WP pin is ignored. When the WPEN bit is set to '1', a LOW on the WP pin inhibits a write to the Status Register. Thus the Status Register is write-protected only when WPEN = '1' and WP = '0'. Table 5 summarizes the write protection conditions. Table 2. Status Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WPEN (0) X (1) X (0) X (0) BP1 (0) BP0 (0) WEL (0) X (0) Table 3. Status Register Bit Definition Bit Definition Description Bit 0 Don’t care This bit is non-writable and always returns ‘0’ upon read. Bit 1 (WEL) Write Enable WEL indicates if the device is write enabled. This bit defaults to ‘0’ (disabled) on power-up. WEL = '1' --> Write enabled WEL = '0' --> Write disabled Bit 2 (BP0) Block Protect bit ‘0’ Used for block protection. For details, see Table 4 on page 7. Bit 3 (BP1) Block Protect bit ‘1’ Used for block protection. For details, see Table 4 on page 7. Bit 4-5 Don’t care These bits are non-writable and always return ‘0’ upon read. Bit 6 Don’t care This bit is non-writable and always returns ‘1’ upon read. Bit 7 (WPEN) Write Protect Enable bit Used to enable the function of Write Protect Pin (WP). For details, see Table 5 on page 7. Table 4. Block Memory Write Protection BP1 BP0 Protected Address Range 0 0 None 0 1 60000h to 7FFFFh (upper 1/4) 1 0 40000h to 7FFFFh (upper 1/2) 1 1 00000h to 7FFFFh (all) Table 5. Write Protection WEL WPEN WP Protected Blocks Unprotected Blocks Status Register 0 X X Protected Protected Protected 1 0 X Protected Unprotected Unprotected 1 1 0 Protected Unprotected Protected 1 1 1 Protected Unprotected Unprotected |
同様の部品番号 - FM25V40 |
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同様の説明 - FM25V40 |
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