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SL74LV244DW データシート(PDF) 4 Page - System Logic Semiconductor |
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SL74LV244DW データシート(HTML) 4 Page - System Logic Semiconductor |
4 / 4 page SL74LV244 4 System Logic Semiconductor SLS AC ELECTRICAL CHARACTERISTICS (C L=50 pF, t r=tf=6.0 ns) Test VCC Guaranteed Limit Symbol Parameter conditions V 25 °C -40 °C to 85 °C 125 °C Unit min max min max min max tPHL, tPLH Propagation delay , 1An to 1Yn, 2An to 2Yn VI = 0 V or VCC Figure 1 and 3 1.2 2.0 * - - - 100 24 15 - - - 125 30 19 - - - 150 36 23 ns tPHZ tPLZ Propagation delay, 1OE to 1Yn, 2OE to 2Yn VI = 0 V or VCC Figure 2 and 4 1.2 2.0 * - - - 140 30 20 - - - 175 35 24 - - - 210 41 28 ns tPZH tPZL Propagation delay, 1OE to 1Yn, 2OE to 2Yn VI = 0 V or VCC Figure 2 and 4 1.2 2.0 * - - - 140 32 20 - - - 175 40 25 - - - 210 48 30 ns tTHL, tTLH Output Transition Time, Any Output VI = 0 V or VCC Figure 1 and 3 1.2 2.0 * - - - 60 16 10 - - - 75 20 13 - - - 90 24 15 ns CI Input capacitance 3.0 - 7.0 - 7.0 - 7.0 pF CPD Power dissipation capacitance (per one channel) VI = 0 V or VCC - 50 - - - - pF * VCC = 3.3 ± 0.3 V Figure 1. Switching Waveforms Figure 2. Switching Waveforms * Includes all probe and jig capacitance * Includes all probe and jig capacitance Figure 3. Test Circuit Figure 4. Test Circuit DEVICE UNDER TEST OUTPUT CL * TEST POINT DEVICE UNDER TEST OUTPUT 1 k CL * TEST POINT Connect to V C C when testing tP LZ and tP ZL Connect to GND when testing tP HZ and tP ZH t t t t PZH PHZ PZL PLZ V V CC OH GND 50% 50% 50% 1OE 2OE or 1Y or 2Y n n 1Y or 2Y n n GND V V OL CC 90% 90% 50% 50% 10% 10% t t t t t t f r PLH TLH THL PHL V CC GND 1A or 2A n n 1Y or 2Y n n |
同様の部品番号 - SL74LV244DW |
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同様の説明 - SL74LV244DW |
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