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ADC08B200 データシート(PDF) 9 Page - Texas Instruments

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部品番号 ADC08B200
部品情報  200 MSPS A/D Converter with Capture Buffer
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メーカー  TI1 [Texas Instruments]
ホームページ  http://www.ti.com
Logo TI1 - Texas Instruments

ADC08B200 データシート(HTML) 9 Page - Texas Instruments

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VA
GND
VIN
TO INTERNAL
CIRCUITRY
ADC08B200
www.ti.com
SNAS388F – MARCH 2007 – REVISED APRIL 2013
CONVERTER TIMING CHARACTERISTICS
The following specifications apply for VA = VDR = +3.3VDC, VRT = +1.9V, VRB = 0.3V, CL = 50 pF, fCLK = 200 MHz at 50% duty
cycle, OEDGE/TEN = 1, Buffer and PLL bypassed. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C
(1) (2)
Units
Parameter
Test Conditions
Typ (3)
Limits (3)
(Limits)
PLL Disabled
210
200
MHz (min)
fC1
Maximum Input Clock Rate
Using PLL
15
105
MHz (min)
PLL Disabled
1
MHz
fC2
Minimum Input Clock Rate
Using PLL
15
MHz
tCL
Minimum CLK Low Time
(4)
1.7
ns (min)
tCH
Minimum CLK High Time
(4)
1.7
ns (min)
fRC1
Maximum RCLK Rate
(5)
210
200
MHz (min)
fRC2
Minimum RCLK Rate
(5)
2
MHz
tRCL
Minimum RCLK Low Time
(4)
2.0
ns (min)
tRCH
Minimum RCLK High Time
(4)
2.0
ns (min)
ΔDC
DRDY to RCLK Duty Cycle Delta
0.3
±3
%
−0.8
ns (min)
tSU
REN to RCLK Set-Up Time
−0.4
4.0
ns (max)
RCLK Rising Edge to DRDY Rising
2.4
ns (min)
tRR
3.8
Edge
5.9
ns (max)
RCLK Falling Edge to DRDY Falling
tRF
3.5
ns
Edge
tSKDR
Skew of DRDY Rising Edge to DATA
160
ps
RCLK Falling Edge to First DATA
1.8
ns (min)
tSKR
2.3
Byte
7.4
ns (max)
Skew of DRDY Rising Edge to EF
tSKEF
36
ps
Rising Edge
tCFF
CLK Rising Edge to FF Rising Edge
4.2
ns
FF Rising Edge to WENSYNC Falling
tFFW
ASW pin high
4.2
ns
Edge
CLK Rising Edge to WENSYNC
2.4
ns (min)
tCW
PLL Disabled
3.5
Rising Edge
5.5
ns (max)
Write Clock
tRST
RESET Pulse Width
(4)
4
Cycles (min)
CL = 10 pF
0.9
ns
Output Data Rise Time
tr
(0.4V to 2.5V)
CL = 20 pF
2
ns
(1)
The analog inputs are protected as shown below. Input voltage magnitudes up to VA + 300 mV or to 300 mV below GND will not
damage this device. However, errors in the A/D conversion can occur if the input goes above VA or below GND by more than 100 mV.
For example, if VA is 3.3VDC the input voltage must be ≤3.4VDC to ensure accurate conversions.
(2)
To ensure accuracy, it is required that VA, VD, VP and VDR be well bypassed. Each supply pin should be decoupled with separate
bypass capacitors.
(3)
Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are specified to Texas Instrument's AOQL
(Average Outgoing Quality Level).
(4)
This parameter is specified by design and/or characterization and is not production tested.
(5)
RCLK should be stopped with the buffer is not being read.
Copyright © 2007–2013, Texas Instruments Incorporated
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