ADC08B200-Q1 datasheet(8/39 Pages) TI1

部品番号	ADC08B200-Q1

部品情報	200 MSPS A/D Converter with Capture Buffer

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ADC08B200

SNAS388F – MARCH 2007 – REVISED APRIL 2013

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CONVERTER ELECTRICAL CHARACTERISTICS (continued)

The following specifications apply for VA = VD = VP = VDR = +3.3VDC, VRT = +1.9V, VRB = 0.3V, CL = 10 pF, fCLK = 200 MHz at

50% duty cycle, OEDGE/TEN = 1, Buffer and PLL bypassed. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ =

25°C

(1)(2)

Units

Parameter

Test Conditions

Typ(3)

Limits (3)

(Limits)

fIN = 10 MHz, VIN = FS − 0.25 dB

−62

dBc

fIN = 49 MHz, VIN = FS − 0.25 dB

−63

dBc

HD3

3rd Harmonic Distortion

fIN = 49 MHz, VIN = FS − 0.25 dB, PLL x8

−62

dBc

fIN = 100 MHz, VIN = FS − 0.25 dB

−56

dBc

fIN = 100 MHz, VIN = FS − 0.25 dB, PLL x4

−54.6

dBc

f1 = 11 MHz, VIN = FS − 6.25 dB

IMD

Intermodulation Distortion

-50

dBc

f2 = 12 MHz, VIN = FS − 6.25 dB

POWER SUPPLY CHARACTERISTICS

DC Input

72.5

mA

IA

Analog Supply Current

fIN = 50 MHz

76.8

88.3

mA (max)

PD High

0.3

mA

DC Input, Buffer bypassed

1.2

mA

fIN = 50 MHz, Buffer bypassed

1.6

2.1

mA (max)

ID

Digital Core Supply Current

fIN = 50 MHz, 1k writing to Buffer

(4)

38

42.4

mA

PDADC High, reading Buffer (4)

1.1

mA

PD High

0.3

mA

PLL x2

8.8

10.1

mA (max)

IP

PLL Supply Current

PLL disabled

3.6

4.3

mA (max)

PD High

60

µA

DC Input

7

mA

IDR

Output Driver Supply Current

fIN = 50 MHz

41

57

mA (max)

PD High

25

µA

DC Input, Buffer bypassed, PLL x2

97.5

mA

(5)

50 MHz Input, writing to Buffer, PLL X2

IA + ID

164.6

198

mA (max)

(5)

+ IP +

Total Operating Current

IDR

PDADC = Hi, reading Buffer,

20

mA

RCLK = 200 MHz, D.C. input

PD High

0.65

mA

DC Input, Buffer & PLL bypassed

306

mW

50 MHz Input, writing to Buffer, PLL X2

543

653

mW (max)

(5)

PC

Power Consumption

PDADC High, reading Buffer, PLL disabled (5)

66

mW

PD High

2.15

mW

D.C. Power Supply Rejection

PSRR1

FSE change with 3.0V to 3.6V change in VA

48

dB

Ratio

A.C. Power Supply Rejection

PSRR2

SNR reduction with 200 mV at 10MHz on supply

TBD

dB

Ratio

(4)

This current or power is used only during the short time that the buffer is being written to or read from, depending upon the specification.

(5)

This current or power is used only during the short time that the buffer is being written to or read from, depending upon the specification.

8

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