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ADC08L060 データシート(PDF) 8 Page - Texas Instruments

部品番号 ADC08L060
部品情報  10 MSPS to 60 MSPS, 0.65 mW/MSPS A/D Converter with Internal Sample-and-Hold
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ホームページ  http://www.ti.com
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ADC08L060 データシート(HTML) 8 Page - Texas Instruments

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THD = 20 x log
+ . . . + A
A
f2
2
f10
2
Af1
2
ADC08L060
SNAS167G – MAY 2002 – REVISED MARCH 2013
www.ti.com
MISSING CODES are those output codes that are skipped and will never appear at the ADC outputs. These
codes cannot be reached with any input value.
MSB (MOST SIGNIFICANT BIT) is the bit that has the largest value or weight. Its value is one half of full scale.
OUTPUT DELAY is the time delay after the rising edge of the input clock before the data update is present at the
output pins.
OUTPUT HOLD TIME is the length of time that the output data is valid after the rise of the input clock.
PIPELINE DELAY (LATENCY) is the number of clock cycles between initiation of conversion and when that data
is presented to the output driver stage. New data is available at every clock cycle, but the data lags the
conversion by the Pipeline Delay plus the Output Delay.
POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well the ADC rejects a change in the power
supply voltage. For the ADC08L060, PSRR1 is the ratio of the change in Full-Scale Error that results from a
change in the d.c. power supply voltage, expressed in dB. PSRR2 is a measure of how well an a.c. signal riding
upon the power supply is rejected and is here defined as
(3)
where SNR0 is the SNR measured with no noise or signal on the supply lines and SNR1 is the SNR measured
with a 1 MHz, 200 mVP-P signal riding upon the supply lines.
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal at the output
to the rms value of the sum of all other spectral components below one-half the sampling frequency, not
including harmonics or d.c.
SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or SINAD) is the ratio, expressed in dB, of the rms value of
the input signal at the output to the rms value of all of the other spectral components below half the clock
frequency, including harmonics but excluding d.c.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the
input signal at the output and the peak spurious signal, where a spurious signal is any signal present in the
output spectrum that is not present at the input.
TOTAL HARMONIC DISTORTION (THD) is the ratio expressed in dB, of the rms total of the first nine harmonic
levels at the output to the level of the fundamental at the output. THD is calculated as
(4)
where Af1 is the RMS power of the fundamental (output) frequency and Af2 through Af10 are the RMS power of
the first 9 harmonic frequencies in the output spectrum.
ZERO SCALE OFFSET ERROR is the error in the input voltage required to cause the first code transition. It is
defined as
VOFF = VZT − VRB
(5)
where VZT is the first code transition input voltage.
2nd HARMONIC DISTORTION (2nd HARM) is the difference, expressed in dB, between the rms power in the
output fundamental frequency and the power in its 2nd harmonic at the output.
3rd HARMONIC DISTORTION (3rd HARM) is the difference, expressed in dB, between the rms power in the
output fundamental frequency and the power in its 3rd harmonic at the output.
8
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Product Folder Links: ADC08L060


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