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SN74ALVCH162525DGG データシート(PDF) 1 Page - Texas Instruments

部品番号 SN74ALVCH162525DGG
部品情報  18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS
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メーカー  TI1 [Texas Instruments]
ホームページ  http://www.ti.com
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SN74ALVCH162525DGG データシート(HTML) 1 Page - Texas Instruments

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FEATURES
DESCRIPTION
DGG OR DL PACKAGE
(TOP VIEW)
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CLKENAB
OEAB
A1
GND
A2
A3
VCC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
A18
OEBA
CLKENBA
SEL
CLKAB
B1
GND
B2
B3
VCC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
VCC
B16
B17
GND
B18
CLK1BA
CLK2BA
Data is stored in the internal registers on the low-to-high transition of the clock (CLK) input, provided that the
SN74ALVCH162525
18-BIT REGISTERED BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES058H – NOVEMBER 1995 – REVISED SEPTEMBER 2004
Member of the Texas Instruments Widebus™
Family
EPIC™ (Enhanced-Performance Implanted
CMOS) Submicron Process
B-Port Outputs Have Equivalent 26-
Ω Series
Resistors, So No External Resistors Are
Required
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Package Option Includes Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
NOTE: For tape-and-reel order entry, the DGGR package is
abbreviated to GR.
This 18-bit universal bus transceiver is designed for
1.65-V to 3.6-V VCC operation.
Data
flow
in
each
direction
is
controlled
by
output-enable (OEAB and OEBA) and clock-enable
(CLKENAB and CLKENBA) inputs. For the A-to-B
data flow, the data flows through a single register.
The B-to-A data can flow through a four-stage
pipeline register path, or through a single register
path, depending on the state of the select (SEL)
input.
appropriate CLKEN inputs are low. The A-to-B data transfer is synchronized to the CLKAB input, and B-to-A data
transfer is synchronized with the CLK1BA and CLK2BA inputs.
The B outputs, which are designed to sink up to 12 mA, include equivalent 26-
Ω resistors to reduce overshoot
and undershoot.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH162525 is characterized for operation from –40
°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, EPIC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1995–2004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.


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