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74ALVC74BQ データシート(PDF) 8 Page - NXP Semiconductors |
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74ALVC74BQ データシート(HTML) 8 Page - NXP Semiconductors |
8 / 20 page 2003 May 26 8 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74ALVC74 AC CHARACTERISTICS SYMBOL PARAMETER TEST CONDITIONS MIN. TYP.(1) MAX. UNIT OTHER VCC (V) Tamb = −40 to +85 °C tPHL/tPLH propagation delay nCP to nQ, nQ see Figs 6 and 8 1.65 to 1.95 1.0 3.7 6.2 ns 2.3 to 2.7 1.0 2.6 4.2 ns 2.7 1.0 2.8 4.2 ns 3.0 to 3.6 1.0 2.7 3.8 ns tPHL/tPLH propagation delay nSD to nQ, nQ see Figs 7 and 8 1.65 to 1.95 1.0 3.4 5.4 ns 2.3 to 2.7 1.0 2.4 3.8 ns 2.7 1.0 3.2 4.2 ns 3.0 to 3.6 1.0 2.3 3.5 ns tPHL/tPLH propagation delay nRD to nQ, nQ see Figs 7 and 8 1.65 to 1.95 1.0 3.5 5.4 ns 2.3 to 2.7 1.0 2.5 3.8 ns 2.7 1.0 3.1 4.3 ns 3.0 to 3.6 1.0 2.3 3.5 ns tW clock pulse width HIGH or LOW see Figs 6 and 8 1.65 to 1.95 2.5 0.9 − ns 2.3 to 2.7 2.5 0.6 − ns 2.7 2.5 1.3 − ns 3.0 to 3.6 2.5 1.3 − ns tW set or reset pulse width LOW see Figs 7 and 8 1.65 to 1.95 2.5 0.9 − ns 2.3 to 2.7 2.5 0.9 − ns 2.7 2.5 1.0 − ns 3.0 to 3.6 2.5 0.7 − ns trem removal time set or reset see Figs 7 and 8 1.65 to 1.95 0.7 −0.2 − ns 2.3 to 2.7 0.7 −0.1 − ns 2.7 0.7 −0.1 − ns 3.0 to 3.6 0.7 −0.1 − ns tsu set-up time nD to nCP see Figs 6 and 8 1.65 to 1.95 1.2 0.6 − ns 2.3 to 2.7 1.2 0.8 − ns 2.7 0.9 0.5 − ns 3.0 to 3.6 0.8 0.4 − ns th hold time nD to nCP see Figs 6 and 8 1.65 to 1.95 0.6 −0.4 − ns 2.3 to 2.7 0.6 −0.3 − ns 2.7 0.7 −0.4 − ns 3.0 to 3.6 0.8 −0.1 − ns |
同様の部品番号 - 74ALVC74BQ |
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同様の説明 - 74ALVC74BQ |
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