データシートサーチシステム |
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DAC101C081 データシート(PDF) 10 Page - Texas Instruments |
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DAC101C081 データシート(HTML) 10 Page - Texas Instruments |
10 / 40 page SCL SDA tHD;STA tLOW tr tHD;DAT tHIGH tf tSU;DAT tSU;STA tSU;STO tf START REPEATED START STOP tHD;STA START tSP tr tBUF OUTPUT VOLTAGE DIGITAL INPUT CODE 0 0 1023 ZE FSE GE = FSE - ZE FSE = GE + ZE 1023 x VREF 1024 10 DAC101C081, DAC101C081Q, DAC101C085 SNVS801B – APRIL 2012 – REVISED JANUARY 2016 www.ti.com Product Folder Links: DAC101C081 DAC101C081Q DAC101C085 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated AC and Timing Characteristics (continued) The following specifications apply for VA = 2.7 V to 5.5 V, VREF = VA, RL = Infinity, CL = 200 pF to GND. All Maximum and Minimum limits apply for TMIN ≤ TA ≤ TMAX and all Typical limits are at TA = 25°C (unless otherwise specified). PARAMETER TEST CONDITIONS(1) MIN TYP(2) MAX(1)(3) UNIT (6) Spike suppression filtering on SCL and SDA will supress spikes that are less than 50ns for standard-fast mode and less than 10ns for hs-mode. trCL1 Rise time of SCL signal after a repeated start condition and after an acknowledge bit. Standard mode 1000 ns Fast mode 20 + 0.1Cb 300 ns High speed mode, Cb = 100 pF 10 80 ns High speed mode, Cb = 400 pF 20 160 ns tfCL Fall time of a SCL signal Standard mode 300 ns Fast mode 20 + 0.1Cb 300 ns High speed mode, Cb = 100 pF 10 40 ns High speed mode, Cb = 400 pF 20 80 ns Cb Capacitive load for each bus line (SCL and SDA) 400 pF tSP Pulse width of spike suppressed(6)(4) Fast mode 50 ns High speed mode 10 toutz SDA output delay (see Section 1.9) Fast mode 87 270 ns High speed mode 38 60 Figure 1. Input / Output Transfer Characteristic Figure 2. Serial Timing Diagram |
同様の部品番号 - DAC101C081_16 |
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同様の説明 - DAC101C081_16 |
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