データシートサーチシステム |
|
SN74SSTVF16859SR データシート(PDF) 5 Page - Texas Instruments |
|
SN74SSTVF16859SR データシート(HTML) 5 Page - Texas Instruments |
5 / 16 page SN74SSTVF16859 13BIT TO 26BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS SCES429B − MARCH 2003 − REVISED FEBRUARY 2004 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics for PC3200 over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC† MIN TYP‡ MAX UNIT VIK II = −18 mA 2.5 V −1.2 V VOH IOH = −100 µA 2.5 V to 2.7 V VDDQ−0.2 V VOH IOH = −8 mA 2.5 V 1.95 V VOL IOL = 100 µA 2.5 V to 2.7 V 0.2 V VOL IOL = 8 mA 2.5 V 0.35 V II All inputs VI = VCC or GND 2.7 V ±5 µA ICC Static standby RESET = GND IO = 0 2.7 V 10 µA ICC Static operating RESET = VCC, VI = VIH(AC) or VIL(AC) IO = 0 2.7 V 25 mA Dynamic operating − clock only RESET = VCC, VI = VIH(AC) or VIL(AC), CLK and CLK switching 50% duty cycle 19 µA/ MHz ICCD Dynamic operating − per each data input RESET = VCC, VI = VIH(AC) or VIL(AC), CLK and CLK switching 50% duty cycle, One data input switching at one-half clock frequency, 50% duty cycle IO = 0 2.6 V 7 µA/ clock MHz/ D input Data inputs VI = VREF ± 310 mV 2.5 3 3.5 Ci§ CLK, CLK VICR = 1.25 V, VI(PP) = 360mV 2.6 V 2.5 3 3.5 pF Ci RESET VI = VCC or GND 2.6 V 2.3 3 3.5 pF † For this test condition, VDDQ always is equal to VCC. ‡ All typical values are at VCC = 2.6 V, TA = 25°C. § Measured at 50-MHz input frequency timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 2.5 V ± 0.2 V† VCC = 2.6 V ± 0.1 V† UNIT MIN MAX MIN MAX UNIT fclock Clock frequency 500 500 MHz tw Pulse duration, CLK, CLK high or low 1 1 ns tact Differential inputs active time (see Note 6) 22 22 ns tinact Differential inputs inactive time (see Note 7) 22 22 ns tsu Setup time Fast slew rate (see Notes 8 and 10) Data before CLK ↑, CLK↓ 0.65 0.65 ns tsu Setup time Slow slew rate (see Notes 9 and 10) Data before CLK ↑, CLK↓ 0.75 0.75 ns th Hold time Fast slew rate (see Notes 8 and 10) Data after CLK ↑, CLK↓ 0.65 0.65 ns th Hold time Slow slew rate (see Notes 9 and 10) Data after CLK ↑, CLK↓ 0.8 0.8 ns † For this test condition, VDDQ always is equal to VCC. NOTES: 6. VREF must be held at a valid input level, and data inputs must be held low for a minimum time of tact max, after RESET is taken high. 7. VREF, data, and clock inputs must be held at valid voltage levels (not floating) for a minimum time of tinact max, after RESET is taken low. 8. For data signal input slew rate ≥1 V/ns. 9. For data signal input slew rate ≥0.5 V/ns and <1 V/ns. 10. CLK, CLK signals input slew rates are ≥1 V/ns. |
同様の部品番号 - SN74SSTVF16859SR |
|
同様の説明 - SN74SSTVF16859SR |
|
|
リンク URL |
プライバシーポリシー |
ALLDATASHEET.JP |
ALLDATASHEETはお客様のビジネスに役立ちますか? [ DONATE ] |
Alldatasheetは | 広告 | お問い合わせ | プライバシーポリシー | リンク交換 | メーカーリスト All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |