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SN74SSTVF16859S8 データシート(PDF) 6 Page - Texas Instruments |
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SN74SSTVF16859S8 データシート(HTML) 6 Page - Texas Instruments |
6 / 16 page SN74SSTVF16859 13BIT TO 26BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS SCES429B − MARCH 2003 − REVISED FEBRUARY 2004 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 switching characteristics for TSSOP over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 2.5 V ± 0.2 V† UNIT PARAMETER (INPUT) (OUTPUT) MIN MAX UNIT fmax 500 MHz tpd‡ CLK and CLK Q 1.1 2.5 ns tPHL RESET Q 5 ns † For this test condition, VDDQ always is equal to VCC. ‡ Single-bit switching switching characteristics for QFN over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 2.5 V ± 0.2 V† VCC = 2.6 V ± 0.1 V† UNIT PARAMETER (INPUT) (OUTPUT) MIN MAX MIN MAX UNIT fmax 500 500 MHz tpd‡ CLK and CLK Q 1.1 2.5 1.1 2.2 ns tPHL RESET Q 5 5 ns † For this test condition, VDDQ always is equal to VCC. ‡ Single-bit switching output slew rates over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER FROM TO VCC = 2.5 V ± 0.2 V† VCC = 2.6 V ± 0.1 V† UNIT PARAMETER FROM TO MIN MAX MIN MAX UNIT dV/dt_r 20% 80% 1 4 1 4 V/ns dV/dt_f 80% 20% 1 4 1 4 V/ns dV/dt_ ∆§ 20% or 80% 80% or 20% 1 1 V/ns † For this test condition, VDDQ always is equal to VCC. § Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate). |
同様の部品番号 - SN74SSTVF16859S8 |
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同様の説明 - SN74SSTVF16859S8 |
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