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CDC318A データシート(PDF) 1 Page - Texas Instruments

部品番号 CDC318A
部品情報  1Line to 10Line Clock Driver
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ホームページ  http://www.ti.com
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CDC318A データシート(HTML) 1 Page - Texas Instruments

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CDC318A
1LINE TO 18LINE CLOCK DRIVER
WITH I2C CONTROL INTERFACE
SCAS614A − SEPTEMBER 1998 − REVISED JUNE 2002
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D High-Speed, Low-Skew 1-to-18 Clock Buffer
for Synchronous DRAM (SDRAM) Clock
Buffering Applications
D Output Skew, tsk(o), Less Than 250 ps
D Pulse Skew, tsk(p), Less Than 500 ps
D Supports up to Four Unbuffered SDRAM
Dual Inline Memory Modules (DIMMs)
D I2C Serial Interface Provides Individual
Enable Control for Each Output
D Operates at 3.3 V
D Distributed VCC and Ground Pins Reduce
Switching Noise
D 100-MHz Operation
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015
D Packaged in 48-Pin Shrink Small Outline
(DL) Package
description
The CDC318A is a high-performance clock buffer
designed to distribute high-speed clocks in PC
applications. This device distributes one input (A)
to 18 outputs (Y) with minimum skew for clock
distribution. The CDC318A operates from a 3.3-V
power supply. It is characterized for operation
from 0
°C to 70°C.
This device has been designed with consideration
for optimized EMI performance. Depending on the
application layout, damping resistors in series to
the clock outputs (like proposed in the PC100
specification) may not be needed in most cases.
The device provides a standard mode (100K-bits/s) I2C serial interface for device control. The implementation
is as a slave/receiver. The device address is specified in the I2C device address table. Both of the I2C inputs
(SDATA and SCLOCK) are 5-V tolerant and provide integrated pullup resistors (typically 140 k
Ω).
Three 8-bit I2C registers provide individual enable control for each of the outputs. All outputs default to enabled
at powerup. Each output can be placed in a disabled mode with a low-level output when a low-level control bit
is written to the control register. The registers are write only and must be accessed in sequential order (i.e.,
random access of the registers is not supported).
The CDC318A provides 3-state outputs for testing and debugging purposes. The outputs can be placed in a
high-impedance state via the output-enable (OE) input. When OE is high, all outputs are in the operational state.
When OE is low, the outputs are placed in a high-impedance state. OE provides an integrated pullup resistor.
Copyright
 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DL PACKAGE
(TOP VIEW)
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NC
NC
VCC
1Y0
1Y1
GND
VCC
1Y2
1Y3
GND
A
VCC
2Y0
2Y1
GND
VCC
2Y2
2Y3
GND
VCC
5Y0
GND
VCC
SDATA
NC
NC
VCC
4Y3
4Y2
GND
VCC
4Y1
4Y0
GND
OE
VCC
3Y3
3Y2
GND
VCC
3Y1
3Y0
GND
VCC
5Y1
GND
GND
SCLOCK
NC − No internal connection


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