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CDC2509CPW データシート(PDF) 5 Page - Texas Instruments

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部品番号 CDC2509CPW
部品情報  3.3V PHASE-LOCK LOOP CLOCK DRIVER
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CDC2509CPW データシート(HTML) 5 Page - Texas Instruments

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CDC2509C
3.3V PHASELOCK LOOP CLOCK DRIVER
SCAS620A − DECEMBER 1998 − REVISED DECEMBER 2004
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC, AVCC
MIN
TYP‡
MAX
UNIT
VIK
Input clamp voltage
II = −18 mA
3 V
−1.2
V
IOH = −100 µA
MIN to MAX
VCC−0.2
VOH
High-level output voltage
IOH = −12 mA
3 V
2.1
V
VOH
High-level output voltage
IOH = − 6 mA
3 V
2.4
V
IOL = 100 µA
MIN to MAX
0.2
VOL
Low-level output voltage
IOL = 12 mA
3 V
0.8
V
VOL
Low-level output voltage
IOL = 6 mA
3 V
0.55
V
VO = 1 V
3.135 V
−32
IOH
High-level output current
VO = 1.65 V
3.3 V
−36
mA
IOH
High-level output current
VO = 3.135 V
3.465 V
−12
mA
VO = 1.95 V
3.135 V
34
IOL
Low-level output current
VO = 1.65 V
3.3 V
40
mA
IOL
Low-level output current
VO = 0.4 V
3.465 V
14
mA
II
Input current
VI = VCC or GND
3.6 V
±5
µA
ICC§
Supply current
VI = VCC or GND,
Outputs: low or high
IO = 0,
3.6 V
10
µA
∆ICC
Change in supply current
One input at VCC − 0.6 V,
Other inputs at VCC or GND
3.3 V to 3.6 V
500
µA
Ci
Input capacitance
VI = VCC or GND
3.3 V
4
pF
Co
Output capacitance
VO = VCC or GND
3.3 V
6
pF
‡ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
§ For ICC of AVCC, and ICC vs Frequency (see Figures 11 and 12).
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 30 pF (see Note 6 and Figures 1 and 2)
PARAMETER
FROM
(INPUT)/CONDITION
TO
(OUTPUT)
VCC, AVCC = 3.3 V
± 0.165 V
UNIT
PARAMETER
(INPUT)/CONDITION
(OUTPUT)
MIN
TYP
MAX
UNIT
Phase error time − static (normalized)
(See Figures 3 − 8)
CLKIN
↑ = 66 MHz to100 MHz
FBIN
−150
150
ps
tsk(o)
Output skew time§
Any Y or FBOUT
Any Y or FBOUT
200
ps
Phase error time − jitter (see Note 7)
Any Y or FBOUT
−50
50
Jitter(cycle-cycle)
(See Figures 9 and 10)
Clkin = 66 MHz to 100 MHz
Any Y or FBOUT
|100|
ps
Duty cycle
F(clkin > 60 MHz)
Any Y or FBOUT
45%
55%
tr
Rise time (See Notes 8 and 9)
VO = 1.2 V to 1.8 V,
IBIS simulation
Any Y or FBOUT
2.5
1
V/ns
tf
Fall time (See Notes 8 and 9)
VO = 1.2 V to 1.8 V,
IBIS simulation
Any Y or FBOUT
2.5
1
V/ns
‡ These parameters are not production tested.
§ The tsk(o) specification is only valid for equal loading of all outputs.
NOTES:
6. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.
7. Calculated per PC DRAM SPEC (tphase error, static − jitter(cycle-to-cycle)).
8. This is equivalent to 0.8 ns/2.5 ns and 0.8 ns/2.7 ns into standard 500
Ω/ 30 pf load for output swing of 04. V to 2 V.
9. 64 MB DIMM configuration according to PC SDRAM Registered DIMM Design Support Document, Figure 20 and Table 13.
Intel is a trademark of Intel Corporation.
PC SDRAM Register DIMM Design Support Document is published by Intel Corporation.


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