データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

AD7266BCP データシート(PDF) 8 Page - Analog Devices

部品番号 AD7266BCP
部品情報  Differential Input, Dual 2 MSPS, 12-Bit, 3-Channel SAR ADC
Download  17 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
Logo AD - Analog Devices

AD7266BCP データシート(HTML) 8 Page - Analog Devices

Back Button AD7266BCP Datasheet HTML 4Page - Analog Devices AD7266BCP Datasheet HTML 5Page - Analog Devices AD7266BCP Datasheet HTML 6Page - Analog Devices AD7266BCP Datasheet HTML 7Page - Analog Devices AD7266BCP Datasheet HTML 8Page - Analog Devices AD7266BCP Datasheet HTML 9Page - Analog Devices AD7266BCP Datasheet HTML 10Page - Analog Devices AD7266BCP Datasheet HTML 11Page - Analog Devices AD7266BCP Datasheet HTML 12Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 8 / 17 page
background image
AD7266
Preliminary Technical Data
TERMINOLOGY
Differential Nonlinearity
Track-and-Hold Acquisition Time
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
The track-and-hold amplifier returns into track mode after the
end of conversion. Track-and-hold acquisition time is the time
required for the output of the track-and-hold amplifier to reach
its final value, within ±1/2 LSB, after the end of conversion.
Integral Nonlinearity
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The
endpoints of the transfer function are zero scale, a point 1 LSB
below the first code transition, and full scale, a point 1 LSB
above the last code transition.
Signal to (Noise + Distortion) Ratio
This is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the sum of all non-fundamental
signals up to half the sampling frequency (fS/2), excluding dc.
The ratio is dependent on the number of quantization levels in
the digitization process; the more levels, the smaller the
quantization noise. The theoretical signal to (noise + distortion)
ratio for an ideal N-bit converter with a sine wave input is given
by:
Offset Error
This applies to Straight Binary output coding. It is the deviation
of the first code transition (00 . . . 000) to (00 . . . 001) from the
ideal, i.e., AGND + 1 LSB.
Offset Error Match
Signal to (Noise + Distortion) = (6.02N + 1.76) dB
This is the difference in Offset Error between the two channels.
Thus for a 12-bit converter, this is 74 dB.
Gain Error
Total Harmonic Distortion
This applies to Straight Binary output coding. It is the deviation
of the last code transition (111 . . . 110) to (111 . . . 111) from the
ideal (i.e., VREF – 1 LSB) after the offset error has been adjusted
out.
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7266 it is defined as:
1
2
6
2
5
2
4
2
3
2
2
log
20
)
(
V
V
V
V
V
V
dB
THD
+
+
+
+
=
Gain Error Match
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5 and V6 are the rms amplitudes of the second through the
sixth harmonics.
This is the difference in Gain Error between the two channels.
Zero Code Error
This applies when using twos complement output coding in
particular with the 2 x VREF input range as –VREF to +VREF biased
about the VREF point. It is the deviation of the midscale
transition (all 1s to all 0s) from the ideal VIN voltage, i.e., VREF - 1
LSB.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it will
be a noise peak.
Zero Code Error Match
This refers to the difference in Zero Code Error between the
two channels.
Channel-to-Channel Isolation
Positive Gain Error
Channel-to-channel isolation is a measure of the level of
crosstalk between channels. It is measured by applying a full-
scale (2 x VREF), 455kHz sine wave signal to all unselected input
channels and determining how much that signal is attenuated in
the selected channel with a 10 kHz signal (0 V to VREF). The
figure given is the worst-case across all twelve channels for the
AD7266.
This applies when using twos complement output coding in
particular with the 2 x VREF input range as –VREF to +VREF biased
about the VREF point. It is the deviation of the last code
transition (011…110) to (011…111) from the ideal (i.e., + VREF -
1 LSB) after the Zero Code Error has been adjusted out.
Rev. PrG | Page 8 of 17


同様の部品番号 - AD7266BCP

メーカー部品番号データシート部品情報
logo
Analog Devices
AD7266BCPZ AD-AD7266BCPZ Datasheet
644Kb / 28P
   Differential/Single-Ended Input, Dual
REV. B
AD7266BCPZ AD-AD7266BCPZ Datasheet
691Kb / 29P
   Differential/Single-Ended Input, Dual 2 MSPS, 12-Bit, 3-Channel SAR ADC
AD7266BCPZ-REEL AD-AD7266BCPZ-REEL Datasheet
644Kb / 28P
   Differential/Single-Ended Input, Dual
REV. B
AD7266BCPZ-REEL AD-AD7266BCPZ-REEL Datasheet
691Kb / 29P
   Differential/Single-Ended Input, Dual 2 MSPS, 12-Bit, 3-Channel SAR ADC
AD7266BCPZ-REEL7 AD-AD7266BCPZ-REEL7 Datasheet
644Kb / 28P
   Differential/Single-Ended Input, Dual
REV. B
More results

同様の説明 - AD7266BCP

メーカー部品番号データシート部品情報
logo
Analog Devices
AD7265 AD-AD7265 Datasheet
706Kb / 16P
   Differential Input, Dual 1 MSPS, 12-Bit, 3-Channel SAR ADC
Rev. PrA
AD7266BSUZ AD-AD7266BSUZ Datasheet
644Kb / 28P
   Differential/Single-Ended Input, Dual 2 MSPS, 12-Bit, 3-Channel SAR ADC
REV. B
AD7266 AD-AD7266_15 Datasheet
889Kb / 29P
   Differential/Single-Ended Input, Dual 2 MSPS, 12-Bit, 3-Channel SAR ADC
REV. B
AD7266 AD-AD7266_17 Datasheet
691Kb / 29P
   Differential/Single-Ended Input, Dual 2 MSPS, 12-Bit, 3-Channel SAR ADC
AD7356 AD-AD7356 Datasheet
191Kb / 18P
   Differential Input, Dual, 5 MSPS, 12-Bit, SAR ADC
Rev. PrC
AD7352 AD-AD7352_17 Datasheet
515Kb / 21P
   Differential Input, Dual, Simultaneous ampling, 3 MSPS, 12-Bit, SAR ADC
AD7352 AD-AD7352 Datasheet
518Kb / 20P
   Differential Input, Dual, Simultaneous Sampling, 3 MSPS, 12-Bit, SAR ADC
REV. 0
AD7352 AD-AD7352_15 Datasheet
623Kb / 21P
   Differential Input, Dual, Simultaneous Sampling, 3 MSPS, 12-Bit, SAR ADC
REV. A
AD7265 AD-AD7265_15 Datasheet
812Kb / 29P
   Differential/Single-Ended Input, Dual 1 MSPS, 12-Bit, 3-Channel SAR ADC
REV. A
AD7265BCPZ AD-AD7265BCPZ Datasheet
690Kb / 28P
   Differential/Single-Ended Input, Dual 1 MSPS, 12-Bit, 3-Channel SAR ADC
REV. A
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17


データシート ダウンロード

Go To PDF Page


リンク URL




プライバシーポリシー
ALLDATASHEET.JP
ALLDATASHEETはお客様のビジネスに役立ちますか?  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com