CDCR83ADBQ datasheet(7/17 Pages) TI1

部品番号	CDCR83ADBQ

部品情報	DIRECT RAMBUS??CLOCK GENERATOR

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SWITCHING CHARACTERISTICS

STATE TRANSITION LATENCY SPECIFICATIONS

CDCR83A

SCAS811 – AUGUST 2005

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP(1)

MAX

UNIT

tc(out)

Clock output cycle time

2.5

3.75

ns

267 MHz

80

300 MHz

70

Total cycle jitter over 1, 2,

Infinite and stopped

t(jitter)

See Figure 3

ps

3, 4, 5, or 6 clock cycles

phase alignment

356 MHz

60

400 MHz

50

t(phase)

Phase detector phase error for distributed loop

Static phase error(2)

–100

100

ps

t(phase, SSC) PLL output phase error when tracking SSC

Dynamic phase error(2)

–100

100

ps

Output duty cycle over 10,000 cycles

See Figure 4

45%

55%

267 MHz

80

300 MHz

70

Output cycle-to-cycle duty

Infinite and stopped

t(DC, err)

See Figure 5

ps

cycle error

phase alignment

356 MHz

60

400 MHz

50

tr, tf

Output rise and fall times (measured at 20%–80% of output

See Figure 7

160

400

ps

voltage)

∆t

Difference between rise and fall times on a single device

See Figure 7

100

ps

(20%–80%) |tf– tr|

(1)

All typical values are at VDD = 3.3 V, TA = 25°C.

(2)

Assured by design

TEST

PARAMETER

FROM

TO

MIN

TYP(1)

MAX

UNIT

CONDITIONS

t(powerup)

Delay time, PWRDNB

↑ to CLK/CLKB out-

See Figure 8

3

put settled (excluding t(DISTLOCK))

Powerdown

Normal

ms

Delay time, PWRDNB

↑ to internal PLL and

3

clock are on and settled

t(VDDpowerup) Delay time, power up to CLK/CLKB output

See Figure 8

3

settled

VDD

Normal

ms

Delay time, power up to internal PLL and

3

clock are on and settled

t(MULT)

MULT0 and MULT1 change to CLK/CLKB

Normal

See Figure 9

1

ms

output resettled (excluding t(DISTLOCK))

t(CLKON)

STOPB

↑ to CLK/CLKB glitch-free clock

See Figure 10

CLK Stop

Normal

10

ns

edges

t(CLKSETL)

STOPB

↑ to CLK/CLKB output settled to

within

CLK Stop

Normal

See Figure 10

20

cycles

50 ps of the phase before STOPB was

disabled

t(CLKOFF)

STOPB

↓ to CLK/CLKB output disabled

Normal

CLK Stop

See Figure 10

5

ns

t(powerdown)

Delay time, PWRDNB

↓ to the device in the

Normal

Powerdown See Figure 8

1

ms

power-down mode

t(STOP)

Maximum time in CLKSTOP (STOPB = 0)

before reentering normal mode

STOPB

Normal

See Figure 10

100

µs

(STOPB = 1)

t(ON)

Minimum time in normal mode

(STOPB = 1) before reentering CLKSTOP

Normal

CLK Stop

See Figure 10

100

ms

(STOPB = 0)

t(DISTLOCK)

Time from when CLK/CLKB output is

settled to when the phase error between

Unlocked

Locked

5

ms

SYNCLKN and PCLKM falls within t(phase)

(1)

All typical values are at VDD = 3.3 V, TA = 25°C.

7

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