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CDCU877AZQLT データシート(PDF) 5 Page - Texas Instruments |
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CDCU877AZQLT データシート(HTML) 5 Page - Texas Instruments |
5 / 24 page www.ti.com Absolute Maximum Ratings (1) Recommended Operating Conditions CDCU877,, CDCU877A 1.8-V PHASE LOCK LOOP CLOCK DRIVER SCAS688D – JUNE 2005 – REVISED JULY 2007 over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage range VDDQ or AVDD –0.5 2.5 V VI Input voltage range(2)(3) –0.5 VDDQ + 0.5 V VO Output voltage range(2)(3) –0.5 VDDQ + 0.5 V IIK Input clamp current VI < 0 or VI > VDDQ ±50 mA IOK Output clamp current VO < 0 or VO > VDDQ ±50 mA IO Continuous output current VO = 0 to VDDQ ±50 mA Continuous current through each VDDQ or GND ±100 mA Tstg Storage temperature range –65 150 °C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. (3) This value is limited to 2.5 V maximum. MIN NOM MAX UNIT Output supply voltage, VDDQ 1.7 1.8 1.9 V VCC Supply Voltage, AVDD (1) VDDQ V VIL Low-level input voltage(2) OE, OS 0.35 x VDDQ V VIH High-level input voltage(2) CK, CK 0.65 x VDDQ V IOH High-level output current (see Figure 2) -9 mA IOL Low-level output current (see Figure 2) 9 mA VIX Input differential-pair cross voltage (VDDQ/2) - 0.15 (VDDQ/2) + 0.15 V VI Input voltage level -0.3 VDDQ + 0.3 V DC 0.3 VDDQ + 0.4 V Input differential voltage(2) VID (see Figure 9 ) AC 0.6 VDDQ + 0.4 V TA Operating free-air temperature -40 85 °C (1) The PLL is turned off and bypassed for test purposes when AVDD is grounded. During this test mode, VDDQ remains within the recommended operating conditions and no timing parameters are specified. (2) VID is the magnitude of the difference between the input level on CK and the input level on CK, see Figure 9 for definition. The CK and CK, VIH and VIL limits define the dc low and high levels for the logic detect state. 5 Submit Documentation Feedback |
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