CDCVF2510APWRG4 datasheet(10/18 Pages) TI1

部品番号	CDCVF2510APWRG4

部品情報	3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

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fc − Clock Frequency at FBOUT − MHz

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VCC = 3.3 V

C(LY) = 25 pF || 500 Ω

C(LF) = 12 pF || 500 Ω

TA = 25°C

See Notes C and D

Cycle to Cycle

25

15

10

5

0

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0

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125

150

175

AVCC = VCC = 3.6 V

Bias = 0/3 V

C(LY) = 25 pF || 500 Ω

C(LF) = 12 pF || 500 Ω

TA = 25°C

See Notes A and B

fc − Clock Frequency − MHz

200

250

150

100

50

0

200

fc − Clock Frequency − MHz

0

25

50

75

100

125

150

175

200

AVCC = VCC = 3.6 V

Bias = 0/3 V

C(LY) = 25 pF || 500 Ω

C(LF) = 12 pF || 500 Ω

TA = 25°C

See Notes A and B

CDCVF2510A

SCAS764C – MARCH 2004 – REVISED FEBRUARY 2009 ............................................................................................................................................... www.ti.com

TYPICAL CHARACTERISTICS (continued)

JITTER

ANALOG SUPPLY CURRENT

vs

CLOCK FREQUENCY AT FBOUT

CLOCK FREQUENCY

Figure 8.

Figure 9.

SUPPLY CURRENT

vs

CLOCK FREQUENCY

Figure 10.

A.

Trace length FBOUT to FBIN = 5 mm, ZO = 50Ω

B.

C(LY) = Lumped capacitive load Y1-n

C.

C(LFx) = Lumped feedback capacitance at FBOUT = FBIN

D.

C(LFx) = Lumped feedback capacitance at FBOUT = FBIN

10

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