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ADC101S101 データシート(PDF) 9 Page - National Semiconductor (TI) |
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ADC101S101 データシート(HTML) 9 Page - National Semiconductor (TI) |
9 / 23 page ADC121S101/ADC101S101/ADC081S101 Timing Specifications The following specifications apply for V DD = +2.7V to 5.25V, fSCLK = 20 MHz, Boldface limits apply for TA = −40˚C to +85˚C: all other limits T A = 25˚C, unless otherwise noted. (Note 11) Symbol Parameter Conditions Typical Limits Units t CONVERT 16xt SCLK t QUIET (Note 7) 50 ns (min) t 1 Minimum CS Pulse Width 10 ns (min) t 2 CS to SCLK Setup Time 10 ns (min) t 3 Delay from CS Until SDATA TRI-STATE® Disabled (Note 8) 20 ns (max) t 4 Data Access Time after SCLK Falling Edge(Note 9) V DD = +2.7 to +3.6 40 ns (max) V DD = +4.75 to +5.25 20 ns (max) t 5 SCLK Low Pulse Width 0.4 x t SCLK ns (min) t 6 SCLK High Pulse Width 0.4 x t SCLK ns (min) t 7 SCLK to Data Valid Hold Time V DD = +2.7 to +3.6 7 ns (min) V DD = +4.75 to +5.25 5 ns (min) t 8 SCLK Falling Edge to SDATA High Impedance (Note 10) V DD = +2.7 to +3.6 25 ns (max) 6 ns (min) V DD = +4.75 to +5.25 25 ns (max) 5 ns (min) t POWER-UP Power-Up Time from Full Power-Down 1µs Note 1: Absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not implied. Exposure to maximum ratings for extended periods may affect device reliability. Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified Note 3: Specification limit guaranteed by design. Note 4: See the section titled "Surface Mount" found in a current National Semiconductor Linear Databook for other methods of soldering suface mount devices. Note 5: Except power supply pins. Note 6: Independent of supply voltage. Note 7: Minimum Quiet Time Required Between Bus Relinquish and Start of Next Conversion Note 8: Measured with the load circuit shown above, and defined as the time taken by the output to cross 1.0V. Note 9: Measured with the load circuit shown above, and defined as the time taken by the output to cross 1.0V or 2.0V. Note 10: t8 is derived from the time taken by the outputs to change by 0.5V with the loading circuit shown above. The measured number is then adjusted to remove the effects of charging or discharging the 25pF capacitor. This means t8 is the true bus relinquish time, independent of the bus loading. Note 11: All input signals are specified as tr =tf = 5 ns (10% to 90% VDD) and timed from 1.6V. www.national.com 9 |
同様の部品番号 - ADC101S101 |
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同様の説明 - ADC101S101 |
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