FDC1004Q

SNOSCZ4 – APRIL 2015

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Feature Description (continued)

In a single ended configuration, such as CINn vs. GND, SHLD1 is internally shorted to SHLD2. In a single ended

configuration, such as CINn vs. GND with CAPDAC enabled, SHLD1 is assigned to the selected channel,

SHLD2 is floating.

For best results, locate the FDC1004Q as close as possible to the capacitive sensor. Minimize the connection

length between the sensor and FDC1004Q CINn pins and between the sensor ground and the FDC1004Q GND

pin. Shield the PCB traces to the CINn pins and connect the shielding to the FDC1004Q SHLDx pins. In addition,

if a shielded cable is used to connect the FDC1004Q to the sensor, the shield should be connected to the

appropriate SHLDx pin. In applications where only one SHLDx pin is used, the unused SHLDx pin can be left

unconnected.

For more information on how to design a sensor with a shield, refer to Capacitive Sensing: Ins and Outs of Active

Sensing application note (SNOA926).

8.3.2 The CAPDAC

The FDC1004Q full-scale input range is ±15 pF. The part can accept a higher capacitance on the input and the

common-mode or offset (constant component) capacitance can be balanced by the programmable on-chip

CAPDACs. The CAPDAC can be viewed as a negative capacitance connected internally to the CINn pin. The

relation between the input capacitance and output data can be expressed as DATA = (CINn – CAPDAC), n =

1...4. The CAPDACs have a 5-bit resolution, monotonic transfer function, are well matched to each other, and

have a defined temperature coefficient.

8.3.3 Capacitive System Offset Calibration

The capacitive offset can be due to many factors including the initial capacitance of the sensor, parasitic

capacitances of board traces, and the capacitance of any other connections between the sensor and the FDC.

The parasitic capacitances of the FDC1004Q are calibrated out at production. If there are other sources of offset

in the system, it may be necessary to calibrate the system capacitance offset in the application. Any offset in the

capacitance input larger than ½ LSB of the CAPDAC should first be removed using the on-chip CAPDACs. Any

residual offset of approximately 1 pF can then be removed by using the capacitance offset calibration register.

The offset calibration register is reloaded by the default value at power-on or after reset. Therefore, if the offset

calibration is not repeated after each system power-up, the calibration coefficient value should be stored by the

host controller and reloaded as part of the FDC1004Q setup.

8.3.4 Capacitive Gain Calibration

The gain is factory calibrated up to ±15 pF in the production for each part individually. The factory gain coefficient

is stored in a one-time programmable (OTP) memory.

The gain can be temporarily changed by setting the Gain Calibration Register (registers 0x11 to 0x14) for the

appropriate CINn pin, although the factory gain coefficient will be restored after power-up or reset.

The part is tested and specified for use only with the default factory calibration coefficient. Adjusting the Gain

calibration can be used to normalize the capacitance measurement of the CINn input channels.

8.4 Device Functional Modes

8.4.1 Single Ended Measurement

The FDC1004Q can be used for interfacing to a single-ended capacitive sensor. In this configuration the sensor

should be connected to the input CINn (n = 1..4) pins of the FDC1004Q and GND. The capacitance-to-digital

convertor (without using the CAPDAC, CAPDAC= 0pF) measures the positive (or the negative) input capacitance

in the range of 0 pF to 15 pF. The CAPDAC can be used for programmable shifting of the input range. In this

case it is possible to measure input capacitance in the range of 0 pF to ±15 pF which are on top of an offset

capacitance up to 100 pF. In single ended measurements with CAPDAC disabled SHLD1 is internally shorted to

SHLD2 (see Figure 10); if CAPDAC is enabled SHLD2 is floating (see Figure 11). The single ended mode is

enabled when the CHB register of the Measurements configuration registers (see Table 4) are set to b100 or

b111.

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