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LM12L458 データシート(PDF) 5 Page - Texas Instruments

部品番号 LM12L458
部品情報  12-Bit Sign Data Acquisition System with Self-Calibration
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メーカー  TI1 [Texas Instruments]
ホームページ  http://www.ti.com
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LM12L458 データシート(HTML) 5 Page - Texas Instruments

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LM12L458
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SNAS085B – JULY 1999 – REVISED MARCH 2013
Converter Characteristics (continued)
The following specifications apply for VA+ = VD+ = +3.3V, VREF+ = +2.5V, VREF− = 0V, 12-bit + sign conversion mode, fCLK =
6.0 MHz, RS = 25Ω, source impedance for VREF+ and VREF− ≤ 25Ω, fully-differential input with fixed 1.25V common-mode
voltage, and minimum acquisition time unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other
limits TA = TJ = 25°C
(1)(2)(3)(4)
Symbol
Parameter
Conditions
Typical(5)
Limits(6)
Units
Zero Error
VA+ = VD+ = +3.3V ±10%
±0.2
±1.75
LSB (max)
Power Supply
PSS
Full-Scale Error
VREF+ = 2.5V, VREF− = GND
±0.4
±2
LSB (max)
Sensitivity(11)
Linearity Error
±0.2
LSB
CREF
VREF+/VREF− Input Capacitance
85
pF
Selected Multiplexer Channel Input
CIN
75
pF
Capacitance
(11) Power Supply Sensitivity is measured after Auto-Zero and/or Auto-Calibration cycle has been completed with VA+ and VD+ at the
specified extremes.
Converter AC Characteristics
The following specifications apply for VA+ = VD+ = +3.3V, VREF+ = +2.5V, VREF− = 0V, 12-bit + sign conversion mode, fCLK =
6.0 MHz, RS = 25Ω, source impedance for VREF+ and VREF− ≤ 25Ω, fully-differential input with fixed +1.25V common-mode
voltage, and minimum acquisition time unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other
limits TA = TJ = 25°C.
(1) (2) (3) (4)
Symbol
Parameter
Conditions
Typical(5)
Limits(6)
Units
40
% (min)
Clock Duty Cycle
50
60
% (max)
13-Bit Resolution, Sequencer State
44 (tCLK)
44 (tCLK) + 50 ns
(max)
S5 (Figure 31)
tC
Conversion Time
9-Bit Resolution, Sequencer State
21 (tCLK)
21 (tCLK) + 50 ns
(max)
S5 (Figure 31)
Sequencer State S7 (Figure 31)
9 (tCLK)
9 (tCLK) + 50 ns
(max)
Built-in minimum for 13-Bits
tA
Acquisition Time
Built-in minimum for 9-Bits and
2 (tCLK)
2 (tCLK) + 50 ns
(max)
“Watchdog” mode
tZ
Auto-Zero Time
Sequencer State S2 (Figure 31)
76 (tCLK)
76 (tCLK) + 50 ns
(max)
tCAL
Full Calibration Time
Sequencer State S2 (Figure 31)
4944 (tCLK)
4944 (tCLK) + 50 ns
(max)
Throughput Rate(7)
107
106
kHz (min)
tWD
Sequencer States S6, S4, and S5
“Watchdog” Mode Comparison Time
11 (tCLK)
11 (tCLK) + 50 ns
(max)
(Figure 31)
tPU
Power-Up Time
10
ms
tWU
Wake-Up Time
10
ms
(1)
Two on-chip diodes are tied to each analog input through a series resistor, as shown below. Input voltage magnitude up to 5V above
VA+ or 5V below GND will not damage the LM12L458. However, errors in the A/D conversion can occur if these diodes are forward
biased by more than 100 mV. As an example, if VA+ is 3.0 VDC, full-scale input voltage must be =3.1 VDC to ensure accurate
conversions. See Figure 3
(2)
VA+ and VD+ must be connected together to the same power supply voltage and bypassed with separate capacitors at each V
+ pin to
assure conversion/comparison accuracy.
(3)
Accuracy is ensured when operating at fCLK = 6 MHz.
(4)
With the test condition for VREF = VREF+ - VREF-given as +2.5V, the 12-bit LSB is 305 µV and the 8-bit/“Watchdog” LSB is 4.88 mV.
(5)
Typical figures are at TA = 25°C and represent most likely parametric norm.
(6)
Limits are specified to AOQL (Average Output Quality Level).
(7)
The Throughput Rate is for a single instruction repeated continuously. Sequencer states 0 (1 clock cycle), 1 (1 clock cycle), 7 (9 clock
cycles) and 5 (44 clock cycles) are used (see Figure 31). One additional clock cycle is used to read the conversion result stored in the
FIFO, for a total of 56 clock cycles per conversion. The Throughput Rate is fCLK (MHz)/N, where N is the number of clock
cycles/conversion.
Copyright © 1999–2013, Texas Instruments Incorporated
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