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LM12L458 データシート(PDF) 7 Page - Texas Instruments

部品番号 LM12L458
部品情報  12-Bit Sign Data Acquisition System with Self-Calibration
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メーカー  TI1 [Texas Instruments]
ホームページ  http://www.ti.com
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LM12L458 データシート(HTML) 7 Page - Texas Instruments

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LM12L458
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SNAS085B – JULY 1999 – REVISED MARCH 2013
Digital Characteristics
The following specifications apply for VA+ = VD+ = +3.3V, unless otherwise specified. Boldface limits apply for TA = TJ =
TMIN to TMAX; all other limits TA = TJ = 25°C.
(1) (2) (3)
Symbol
Parameter
Conditions
Typical(4)
Limits(5)
Units
VIN(1)
Logical “1” Input Voltage
VA+ = VD+ = +3.6V
2.0
V (min)
VA+ = VD+ = +3.0V ALE,
0.7
VIN(0)
Logical “0” Input Voltage
V (max)
Pin 22
0.6
1.0
μA (max)
IIN(1)
Logical “1” Input Current
VIN = +3.3V
0.005
2.0
μA (max)
−1.0
IIN(0)
Logical “0” Input Current
VIN = 0V
−0.005
μA (max)
−2.0
CIN
D0–D15 Input Capacitance
6
pF
VA+ = VD+ = 3.0V
VOUT(1)
Logical “1” Output Voltage
IOUT = −360 μA
2.4
V (min)
IOUT = −10 μA
2.85
V (min)
VA+ = VD+ = +3.0V
VOUT(0)
Logical “0” Output Voltage
IOUT = 1.6 mA
0.4
V (max)
IOUT = 10 μA
0.1
V (max)
VOUT = 0V
−0.01
−3.0
μA (max)
IOUT
TRI-STATE Output Leakage Current
VOUT = +3.3V
0.01
3.0
μA (max)
(1)
Two on-chip diodes are tied to each analog input through a series resistor, as shown below. Input voltage magnitude up to 5V above
VA+ or 5V below GND will not damage the LM12L458. However, errors in the A/D conversion can occur if these diodes are forward
biased by more than 100 mV. As an example, if VA+ is 3.0 VDC, full-scale input voltage must be =3.1 VDC to ensure accurate
conversions. See Figure 3
(2)
VA+ and VD+ must be connected together to the same power supply voltage and bypassed with separate capacitors at each V
+ pin to
assure conversion/comparison accuracy.
(3)
Accuracy is ensured when operating at fCLK = 6 MHz.
(4)
Typical figures are at TA = 25°C and represent most likely parametric norm.
(5)
Limits are specified to AOQL (Average Output Quality Level).
Digital Timing Characteristics
The following specifications apply for VA+ = VD+ = +3.3V, tr = tf = 3 ns, and CL = 100 pF on data I/O, INT and DMARQ lines
unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25°C.
(1) (2) (3)
Symbol (See
Figure 28 Figure 29
Parameter
Conditions
Typical(4)
Limits(5)
Units
Figure 30)
1, 3
CS or Address Valid to ALE Low Set-Up Time
40
ns (min)
2, 4
CS or Address Valid to ALE Low Hold Time
20
ns (min)
5
ALE Pulse Width
45
ns (min)
6
RD High to Next ALE High
35
ns (min)
7
ALE Low to RD Low
20
ns (min)
8
RD Pulse Width
100
ns (min)
9
RD High to Next RD or WR Low
100
ns (min)
10
ALE Low to WR Low
20
ns (min)
11
WR Pulse Width
60
ns (min)
12
WR High to Next ALE High
75
ns (min)
13
WR High to Next RD or WR Low
140
ns (min)
(1)
Two on-chip diodes are tied to each analog input through a series resistor, as shown below. Input voltage magnitude up to 5V above
VA+ or 5V below GND will not damage the LM12L458. However, errors in the A/D conversion can occur if these diodes are forward
biased by more than 100 mV. As an example, if VA+ is 3.0 VDC, full-scale input voltage must be =3.1 VDC to ensure accurate
conversions. See Figure 3
(2)
VA+ and VD+ must be connected together to the same power supply voltage and bypassed with separate capacitors at each V
+ pin to
assure conversion/comparison accuracy.
(3)
Accuracy is ensured when operating at fCLK = 6 MHz.
(4)
Typical figures are at TA = 25°C and represent most likely parametric norm.
(5)
Limits are specified to AOQL (Average Output Quality Level).
Copyright © 1999–2013, Texas Instruments Incorporated
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