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AD0345BS8500RF データシート(PDF) 8 Page - Texas Instruments |
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AD0345BS8500RF データシート(HTML) 8 Page - Texas Instruments |
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8 / 61 page  SMJ320C6701-SP SGUS030F – APRIL 2000 – REVISED SEPTEMBER 2013 www.ti.com Signal Descriptions SIGNAL TYPE(1) DESCRIPTION NAME NO. CLOCK/PLL CLKIN A14 I Clock Input CLKOUT1 Y6 O Clock output at full device speed CLKOUT2 V9 O Clock output at half of device speed CLKMODE1 B17 Clock mode select I CLKMODE0 C17 • Selects whether the output clock frequency = input clock freq ×4 or ×1 PLLFREQ3 C13 PLL frequency range (3, 2, and 1) PLLFREQ2 G11 I • The target range for CLKOUT1 frequency is determined by the 3–bit value of the PLLFREQ pins. PLLFREQ1 F11 PLLV(2) D12 A(3) PLL analog VCC connection for the low-pass filter PLLG(2) G10 A(3) PLL analog GND connection for the low-pass filter PLLF C12 A(3) PLL low-pass filter connection to external components and a bypass capacitor JTAG EMULATION TMS K19 I JTAG test port mode select (features an internal pull-up) TDO R12 O/Z JTAG test port data out TDI R13 I JTAG test port data in (features an internal pull-up) TCK M20 I JTAG test port clock TRST N18 I JTAG test port reset (features an internal pull-down) EMU1 R20 I/O/Z Emulation pin 1, pullup with a dedicated 20-k Ω resistor(4) EMU0 T18 I/O/Z Emulation pin 0, pullup with a dedicated 20-k Ω resistor(4) RESET AND INTERRUPTS RESET J20 I Device reset Nonmaskable interrupt NMI K21 I • Edge driven (rising edge) EXT_INT7 R16 External interrupts EXT_INT6 P20 I EXT_INT5 R15 • Edge driven (rising edge) EXT_INT4 R18 IACK R11 O Interrupt acknowledge for all active interrupts serviced by the CPU INUM3 T19 Active interrupt identification number INUM2 T20 • Valid during IACK for all active interrupts (not just external) O INUM1 T14 • Encoding order follows the interrupt service fetch packet ordering. INUM0 T16 LITTLE ENDIAN/BIG ENDIAN If high, selects little-endian byte/half-word addressing order within a word. LENDIAN G20 I If low, selects big-endian addressing. POWER-DOWN STATUS PD D19 O Power-down mode 2 or 3 (active if high) (1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground (2) PLLV and PLLG signals are not part of external voltage supply or ground. See the CLOCK/PLL documentation for information on how to connect those pins. (3) A = Analog signal (PLL filter) (4) For emulation and normal operation, pull up EMU1 and EMU0 with a dedicated 20-k Ω resistor. For boundary scan, pull down EMU1 and EMU0 with a dedicated 20-k Ω resistor. 8 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: SMJ320C6701-SP |
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