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LM25056A データシート(PDF) 10 Page - Texas Instruments |
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LM25056A データシート(HTML) 10 Page - Texas Instruments |
10 / 39 page LM25056 +12V GND VIN ENABLE SHUTDOWN CONTROL LM25056A SNVS785A – JANUARY 2011 – REVISED APRIL 2013 www.ti.com FUNCTIONAL DESCRIPTION The LM25056A provides intelligent monitoring of the input voltage, input current, input power, temperature, and an auxiliary input. The LM25056A also provides a peak capture of the input power and programmable hardware averaging of the input voltage, current, power, temperature, and the auxiliary voltage. Warning thresholds which trigger the SMBA pin may be programmed for input and auxiliary voltage, current, power, and temperature via the PMBus interface. Enabling/Disabling and Resetting The LM25056A has an ENABLE pin that can be used to power on and off the device. If desired, the LM25056A can be kept in shutdown until the supply reaches a particular threshold using ENABLE with a resistor divider or with an active control as shown in Figure 15. Figure 15. ENABLE Control When taken low, this logic pin will reduce the quiescent current for the device and will no longer respond to PMBus commands. Also, taking the ENABLE low is a functional reset of the LM25056A. Raising ENABLE sets the part to its default operation. If this functionality is not used, then ENABLE should be left floating (an internal pull-up will maintain its operation) or tied to an external VDD voltage. Do not tie ENABLE to the onboard VDD. The VDD power-up is delayed and when power is first applied, and VDD starts low. This in turn will keep ENABLE low and the LM25056A will not start up. VDD and VREF also have a power-on-reset (POR) circuit that holds the LM25056A in reset until it reaches the operating state. Note that if either of these output lines are inadvertently pulled low, the device is reset to its initial default state, erasing the volatile memory the same as ENABLE pulled low. Once VDD and VREF have reached the POR threshold of 2.4V, the device comes out of reset. As an example, the SMBus address of the LM25056A is captured based on the states (GND, NC, VDD) of the ADR0, ADR1, and ADR2 pins during turn on and is latched into a volatile register once the ENABLE pin is determined to be high and the VDD and VREF has exceeded its POR threshold of 2.4V. Reassigning or postponing the address capture can be accomplished by holding the ENABLE pin to AGND. For more information on the operation of these pins, please see the PMBus Address Lines section of this datasheet. The logic and volatile memory can also be reset with a PMBus write to the MFR_DEVICE_SETUP (D9h) register into the software reset bit. However, this software reset will not trigger a read of the states of the address pins as the ENABLE pin or VDD and VREF POR events will. VDD Sub-Regulator The LM25056A contains an internal linear sub-regulator which steps down the input voltage to generate a 3.7V rail used for powering low voltage and low power circuitry. When the input voltage is below 3.7V, VDD will track VIN. For input voltages 3.3V and below, VDD should be tied directly to VIN to avoid the dropout of the sub- regulator. The VDD sub-regulator should be used as the pull-up supply for the ADR2, ADR1, and ADR0 pins if they are to be tied high. It may also be used as the pull-up supply for SMBus signals (SDA, SCL, SMBA). The VDD sub-regulator is not designed to drive high currents and should not be loaded to drive high current circuits. The VDD pin is current limited to 50 mA in order to protect the LM25056A in the event of a short. The sub- regulator requires a ceramic bypass capacitance of 1 µF or greater to be placed as close to VDD as the PCB layout allows. 10 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM25056A |
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同様の説明 - LM25056A |
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