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SM320C6457-HIREL データシート(PDF) 4 Page - Texas Instruments |
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SM320C6457-HIREL データシート(HTML) 4 Page - Texas Instruments |
4 / 209 page TCP2_B Serial Rapid I/O DDR2 Mem Ctlr Device Configuration Logic 64 L1P SRAM/Cache Direct-Mapped 32K Bytes L1D SRAM/Cache 2-Way Set-Associative 32K Bytes Total C6457 PLL1 and PLL1 Controller EMIFA HI Boot Configuration I/O Devices UTOPIA I2C GPIO16 16 McBSP0 L2 Cache Memory 2048K Bytes TCP2_A McBSP1 HPI (32/16) DDR2 SDRAM 32 LO Timer1 (A) HI LO Timer0 (A) PLL2 EDMA 3.0 C64x+ DSP Core Data Path B B Register File B31−B16 B15−B0 Instruction Fetch Data Path A A Register File A31−A16 A15−A0 .L1 .S1 .M1 xx xx .D1 .D2 .M2 xx xx .S2 .L2 M e g a m o d u l e L1P Memory Controller (Memory Protect/Bandwidth Mgmt) Instruction Decode 16-/32-bit Instruction Dispatch Control Registers In-Circuit Emulation SPLOOP Buffer L1D Memory Controller (Memory Protect/Bandwidth Mgmt) Secondary Switched Central Resource VCP2 L3 ROM EMAC 10/100/1000 SGMII MDIO 4 SM320C6457-HIREL SPRS948 – JULY 2016 www.ti.com Submit Documentation Feedback Product Folder Links: SM320C6457-HIREL Device Overview Copyright © 2016, Texas Instruments Incorporated 1.5 Functional Block Diagram Figure 1-1 Shows the functional block diagram of the SM320C6457-HIREL device. Figure 1-1. Functional Block Diagram (A) Each of the TIMER peripherals (TIMER1 and TIMER0) is configurable as either one 64-bit general-purpose timer or two 32-bit general- purpose timers or a watchdog timer. |
同様の部品番号 - SM320C6457-HIREL |
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同様の説明 - SM320C6457-HIREL |
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