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SN74F109DR データシート(PDF) 3 Page - Texas Instruments |
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SN74F109DR データシート(HTML) 3 Page - Texas Instruments |
3 / 15 page SN54F109, SN74F109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SDFS047A – MARCH 1987 – REVISED OCTOBER 1993 2–3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS SN54F109 SN74F109 UNIT PARAMETER TEST CONDITIONS MIN TYP† MAX MIN TYP† MAX UNIT VIK VCC = 4.5 V, II = – 18 mA – 1.2 – 1.2 V VOH VCC = 4.5 V, IOH = – 1 mA 2.5 3.4 2.5 3.4 V VOH VCC = 4.75 V, IOH = – 1 mA 2.7 V VOL VCC = 4.5 V, IOL = 20 mA 0.3 0.5 0.3 0.5 V II VCC = 5.5 V, VI = 7 V 0.1 0.1 mA IIH VCC = 5.5 V, VI = 2.7 V 20 20 µA IIL J, K, CLK VCC =5 5V VI =0 5V – 0.6 – 0.6 mA IIL PRE or CLR VCC = 5.5 V, VI = 0.5 V – 1.8 – 1.8 mA IOS‡ VCC = 5.5 V, VO = 0 –60 –150 –60 –150 mA ICC VCC = 5.5 V, See Note 2 11.7 17 11.7 17 mA † All typical values are at VCC = 5 V, TA = 25°C. ‡ Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. NOTE 2: ICC is measured with J, K, CLK, and PRE grounded then with J, K, CLK, and CLR grounded. timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) VCC = 5 V, TA = 25°C SN54F109 SN74F109 UNIT ′F74 UNIT MIN MAX MIN MAX MIN MAX fclock Clock frequency 0 100 0 70 0 90 MHz t Pulse duration CLK high, PRE or CLR low 4 4 4 ns tw Pulse duration CLK low 5 5 5 ns Setup time data before CLK ↑ High 3 3 3 tsu Setup time, data before CLK ↑ Low 3 3 3 ns su Setup time, inactive-state before CLK ↑§ PRE or CLR to CLK 2 2 2 th Hold time data after CLK ↑ High 1 1 1 ns th Hold time, data after CLK ↑ Low 1 1 1 ns § Inactive-state setup time is also referred to as recovery time. switching characteristics (see Note 3) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 5 V, CL = 50 pF, RL = 500 Ω, TA = 25°C VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX¶ UNIT (INPUT) (OUTPUT) ′F109 SN54F109 SN74F109 MIN TYP MAX MIN MAX MIN MAX fmax 100 150 70 90 MHz tPLH CLK QorQ 3 4.9 7 3 9 3 8 ns tPHL CLK Q or Q 3.6 5.8 8 3.6 10.5 3.6 9.2 ns tPLH PRE or CLR QorQ 2.4 4.8 7 2.4 9 2.4 8 ns tPHL PRE or CLR Q or Q 2.7 6.6 9 2.7 11.5 2.7 10.5 ns ¶ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. NOTE 3: Load circuits and waveforms are shown in Section 1. |
同様の部品番号 - SN74F109DR |
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同様の説明 - SN74F109DR |
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