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LM3633 データシート(PDF) 7 Page - Texas Instruments |
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LM3633 データシート(HTML) 7 Page - Texas Instruments |
7 / 59 page t4 t2 t3 t5 t1 SCL SDA_IN SDA_OUT LM3633 www.ti.com SNVS867 – JUNE 2014 6.6 Timing Requirements Limits apply over the full operating ambient temperature range ( −40°C ≤ TA ≤ 85°C) and VIN = 3.6 V, unless otherwise specified. (1) (2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT I2C-COMPATIBLE TIMING SPECIFICATIONS (SCL, SDA)(3), Figure 1 t1 SCL (Clock Period) 2.7 V ≤ VIN ≤ 5.5 V 2.5 µs t2 Data In setup time to SCL high 2.7 V ≤ VIN ≤ 5.5 V 100 t3 Data out stable after SCL low 2.7 V ≤ VIN ≤ 5.5 V 0 ns t4 SDA low setup time to SCL low (Start) 2.7 V ≤ VIN ≤ 5.5 V 100 t5 SDA high hold time after SCL high (Stop) 2.7 V ≤ VIN ≤ 5.5 V 100 INTERNAL POR THRESHOLD AND HWEN TIMING SPECIFICATION VIN ramp time = 100 μs 1.7 2.1 VPOR POR reset release voltage threshold V VIN ramp time = 100 μs, TA = 25°C 1.9 POR reset complete, 2.7 V ≤ VIN ≤ 5.5 20 V tHWEN First I2C start pulse after HWEN high µs POR reset complete, TA = 25°C 5 (1) All voltages are with respect to the potential at the GND pin. (2) Minimum and Maximum limits are verified by design, test, or statistical analysis. Typical (Typ) numbers are not verified, but do represent the most likely norm. Unless otherwise specified, conditions for typical specifications are: VIN = 3.6 V and TA = 25°C. (3) SCL and SDA must be glitch-free in order for proper brightness control to be realized. Figure 1. I2C-Compatible Interface Timing Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: LM3633 |
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