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SN74AUP1G00DRLRG4 データシート(PDF) 4 Page - Texas Instruments

部品番号 SN74AUP1G00DRLRG4
部品情報  Low-Power Single 2-Input Positive-NAND Gate
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ホームページ  http://www.ti.com
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SN74AUP1G00
SCES604I – SEPTEMBER 2004 – REVISED JUNE 2014
www.ti.com
7 Specifications
7.1 Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCC
Supply voltage range
–0.5
4.6
V
VI
Input voltage range(2)
–0.5
4.6
V
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
4.6
V
VO
Output voltage range in the high or low state(2)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
50
mA
IOK
Output clamp current
VO < 0
50
mA
IO
Continuous output current
20
mA
Continuous current through VCC or GND
50
mA
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
7.2 Handling Ratings
MIN
MAX
UNIT
Tstg
Storage temperature range
–65
150
°C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
0
2000
pins(1)
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification
0
1000
JESD22-C101, all pins(2)
(1)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2)
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
4
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