1

7

1A

1Y

3

5

2A

2Y

6

2

3A

3Y

SN74AUP3G34

SCES766C

– DECEMBER 2009 – REVISED FEBRUARY 2012

www.ti.com

NanoStar

™ package technology is a major breakthrough in IC packaging concepts, using the die as the

package.

preventing damaging current backflow through the device when it is powered down.

ORDERABLE

TOP-SIDE

PART NUMBER

NanoStar

™ – WCSP (DSBGA)

Reel of 3000

SN74AUP3G34YFPR

_ _ H 9 _

0.23-mm Large Bump

– YFP (Pb-free)

uQFN

– DQE

Reel of 5000

SN74AUP3G34DQER

TZ

–40°C to 85°C

QFN

– RSE

Reel of 5000

SN74AUP3G34RSER

TZ

SN74AUP3G34DCUR

SSOP

– DCU

Reel of 3000

H34_

SN74AUP3G34DCURG4

(1)

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2)

Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

(3)

DCU: The actual top-side marking has one additional character that designates the wafer fab/assembly site.

YFP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following

character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb,

• = Pb-free).

FUNCTION TABLE

INPUT

OUTPUT

A

Y

H

H

L

L

LOGIC DIAGRAM (POSITIVE LOGIC)

Pin numbers shown are for the DCU and DQE packages.

2

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© 2009–2012, Texas Instruments Incorporated

Product Folder Link(s): SN74AUP3G34