SN54LV273, SN74LV273

OCTAL DTYPE FLIPFLOPS

WITH CLEAR

SCLS195B − FEBRUARY 1993 − REVISED APRIL 1996

4

POST OFFICE BOX 655303

POST OFFICE BOX 1443

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

VCC†

SN54LV273

SN74LV273

UNIT

PARAMETER

TEST CONDITIONS

VCC†

MIN

TYP

MAX

MIN

TYP

MAX

UNIT

IOH = − 100 µA

MIN to MAX

VCC −0.2

VCC −0.2

VOH

IOH = − 6 mA

3 V

2.4

2.4

V

VOH

IOH = −12 mA

4.5 V

3.6

3.6

V

IOL = 100 µA

MIN to MAX

0.2

0.2

VOL

IOL = 6 mA

3 V

0.4

0.4

V

VOL

IOL = 12 mA

4.5 V

0.55

0.55

V

II

VI = VCC or GND

3.6 V

±1

±1

A

II

VI = VCC or GND

5.5 V

±1

±1

µA

IOZ

VO = VCC or GND,

IO = 0

3.6 V

±5

±5

A

IOZ

VO = VCC or GND,

IO = 0

5.5 V

±5

±5

µA

ICC

VI = VCC or GND,

IO = 0

3.6 V

20

20

A

ICC

VI = VCC or GND,

IO = 0

5.5 V

20

20

µA

nICC

One input at VCC − 0.6 V,

Other inputs at VCC or GND

3 V to 3.6 V

500

500

µA

Ci

VI = VCC or GND

3.3 V

2.5

2.5

pF

Ci

VI = VCC or GND

5 V

3

3

pF

† For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions.

timing requirements over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted)

SN54LV273

VCC = 5.5 V

± 0.5 V

VCC = 3.3 V

± 0.3 V

VCC = 2.7 V

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

fclock

Clock frequency

0

60

0

50

0

40

MHz

tw

Pulse duration

CLR low

6

10

12

ns

tw

Pulse duration

CLK high or low

7

10

12

ns

tsu

Setup time before CLK

↑

Data

8

12

14

ns

tsu

Setup time before CLK

↑

CLR inactive

2

2

2

ns

th

Hold time, data after CLK

↑

3

2

2

ns

timing requirements over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted)

SN74LV273

VCC = 5.5 V

± 0.5 V

VCC = 3.3 V

± 0.3 V

VCC = 2.7 V

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

fclock

Clock frequency

0

60

0

50

0

40

MHz

tw

Pulse duration

CLR low

6

10

12

ns

tw

Pulse duration

CLK high or low

7

10

12

ns

tsu

Setup time before CLK

↑

Data

8

12

14

ns

tsu

Setup time before CLK

↑

CLR inactive

2

2

2

ns

th

Hold time, data after CLK

↑

3

2

2

ns

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.